Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/65931?usp=email )
Change subject: arch-arm: Setup TC/ISA at construction time 2nd attempt
......................................................................
arch-arm: Setup TC/ISA at construction time 2nd attempt
This partly reverts commit ec75787aef56665e893d70293bf3a0f93c33bb6a
by fixing the original problem noted by Bobby (long regressions):
setupThreadContext has to be implemented otherswise the GICv3 cpu interface
will end up holding old references when switching TC/ISAs.
This new implementation is still setting up the cpu interface reference
in the ISA only when it is required, but it is storing the
TC/ISA reference within the interface every time the ISA::setupThreadContext
gets called.
Change-Id: I2f54f95761d63655162c253e887b872f3718c764
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65931
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
Maintainer: Bobby Bruce <bbr...@ucdavis.edu>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
5 files changed, 59 insertions(+), 16 deletions(-)
Approvals:
kokoro: Regressions pass
Bobby Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a30fd94..543e0eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -524,15 +524,10 @@
selfDebug->init(tc);
- Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
- if (!gicv3)
- return;
-
- if (!gicv3CpuInterface)
- gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
- gicv3CpuInterface->setISA(this);
- gicv3CpuInterface->setThreadContext(tc);
+ if (auto gicv3_ifc = getGICv3CPUInterface(tc); gicv3_ifc) {
+ gicv3_ifc->setISA(this);
+ gicv3_ifc->setThreadContext(tc);
+ }
}
void
@@ -2008,10 +2003,28 @@
BaseISADevice &
ISA::getGICv3CPUInterface()
{
- panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
+ if (gicv3CpuInterface)
+ return *gicv3CpuInterface.get();
+
+ auto gicv3_ifc = getGICv3CPUInterface(tc);
+ panic_if(!gicv3_ifc, "The system does not have a GICv3 irq
controller\n");
+ gicv3CpuInterface.reset(gicv3_ifc);
+
return *gicv3CpuInterface.get();
}
+BaseISADevice*
+ISA::getGICv3CPUInterface(ThreadContext *tc)
+{
+ assert(system);
+ Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
+ if (gicv3) {
+ return gicv3->getCPUInterface(tc->contextId());
+ } else {
+ return nullptr;
+ }
+}
+
bool
ISA::inSecureState() const
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1f7a756..9e1afa7 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -116,6 +116,7 @@
BaseISADevice &getGenericTimer();
BaseISADevice &getGICv3CPUInterface();
+ BaseISADevice *getGICv3CPUInterface(ThreadContext *tc);
RegVal miscRegs[NUM_MISCREGS];
const RegId *intRegMap;
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index dde3818..e14d1f2 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -147,7 +147,7 @@
for (int i = 0; i < threads; i++) {
redistributors[i] = new Gicv3Redistributor(this, i);
- cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
+ cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
}
distRange = RangeSize(params().dist_addr,
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 0e1dbaa..28a1739 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -55,15 +55,19 @@
const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
-Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
+Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
: BaseISADevice(),
gic(gic),
redistributor(nullptr),
distributor(nullptr),
- cpuId(cpu_id)
+ tc(_tc),
+ maintenanceInterrupt(gic->params().maint_int->get(tc)),
+ cpuId(tc->contextId())
{
hppi.prio = 0xff;
hppi.intid = Gicv3::INTID_SPURIOUS;
+
+ setISA(static_cast<ISA*>(tc->getIsaPtr()));
}
void
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index e860373..ff476bc 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -68,10 +68,10 @@
Gicv3 * gic;
Gicv3Redistributor * redistributor;
Gicv3Distributor * distributor;
- uint32_t cpuId;
- ArmInterruptPin *maintenanceInterrupt;
ThreadContext *tc;
+ ArmInterruptPin *maintenanceInterrupt;
+ uint32_t cpuId;
BitUnion64(ICC_CTLR_EL1)
Bitfield<63, 20> res0_3;
@@ -359,7 +359,7 @@
void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
public:
- Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
+ Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);
void init();
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2f54f95761d63655162c253e887b872f3718c764
Gerrit-Change-Number: 65931
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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