Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66852?usp=email )
Change subject: util: Fix missing include of sim/core.hh in util-tlm
......................................................................
util: Fix missing include of sim/core.hh in util-tlm
Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M util/tlm/src/sc_master_port.cc
1 file changed, 11 insertions(+), 0 deletions(-)
diff --git a/util/tlm/src/sc_master_port.cc b/util/tlm/src/sc_master_port.cc
index 2e10828..c0bb6d5 100644
--- a/util/tlm/src/sc_master_port.cc
+++ b/util/tlm/src/sc_master_port.cc
@@ -36,6 +36,7 @@
#include "params/ExternalMaster.hh"
#include "sc_ext.hh"
#include "sc_master_port.hh"
+#include "sim/core.hh"
#include "sim/system.hh"
namespace Gem5SystemC
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6dbf71dac903a660369bf8b33ae0c88d28d07457
Gerrit-Change-Number: 66852
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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