Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67074?usp=email )
Change subject: arch-vega: Implement ds_add_f32 atomic
......................................................................
arch-vega: Implement ds_add_f32 atomic
This instruction does an atomic add of a 32-bit float with a VGPR and
value in LDS atomically without return.
Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 5332687..a0308c8 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34749,6 +34749,10 @@
: Inst_DS(iFmt, "ds_add_f32")
{
setFlag(F32);
+ setFlag(MemoryRef);
+ setFlag(GroupSegment);
+ setFlag(AtomicAdd);
+ setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_F32
Inst_DS__DS_ADD_F32::~Inst_DS__DS_ADD_F32()
@@ -34757,15 +34761,54 @@
// --- description from .arch file ---
// 32b:
- // tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
- // RETURN_DATA = tmp.
// Floating point add that handles NaN/INF/denormal values.
void
Inst_DS__DS_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
{
- panicUnimplemented();
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (gpuDynInst->exec_mask.none()) {
+ wf->decLGKMInstsIssued();
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandF32 data(gpuDynInst, extData.DATA0);
+
+ addr.read();
+ data.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemF32*>(gpuDynInst->a_data))[lane]
+ = data[lane];
+ }
+ }
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+ void
+ Inst_DS__DS_ADD_F32::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initAtomicAccess<VecElemF32>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_ADD_F32::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
// --- Inst_DS__DS_WRITE_B8 class methods ---
Inst_DS__DS_WRITE_B8::Inst_DS__DS_WRITE_B8(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 33be33e..05a0002 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31895,6 +31895,8 @@
}
} // getOperandSize
+ void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+ void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_F32
--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/67074?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id4f23a1ab587a23edfd1d88ede1cbcc5bdedc0cb
Gerrit-Change-Number: 67074
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
