Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67075?usp=email )
Change subject: arch-vega: Implement ds_add_u64
......................................................................
arch-vega: Implement ds_add_u64
This instruction does an atomic add of an unsigned 64-bit data with a
VGPR and value in LDS atomically without return.
Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67075
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 3d9808a..a54f426 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -36088,6 +36088,10 @@
Inst_DS__DS_ADD_U64::Inst_DS__DS_ADD_U64(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u64")
{
+ setFlag(MemoryRef);
+ setFlag(GroupSegment);
+ setFlag(AtomicAdd);
+ setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U64
Inst_DS__DS_ADD_U64::~Inst_DS__DS_ADD_U64()
@@ -36096,14 +36100,53 @@
// --- description from .arch file ---
// 64b:
- // tmp = MEM[ADDR];
// MEM[ADDR] += DATA[0:1];
- // RETURN_DATA[0:1] = tmp.
void
Inst_DS__DS_ADD_U64::execute(GPUDynInstPtr gpuDynInst)
{
- panicUnimplemented();
+ Wavefront *wf = gpuDynInst->wavefront();
+
+ if (gpuDynInst->exec_mask.none()) {
+ wf->decLGKMInstsIssued();
+ return;
+ }
+
+ gpuDynInst->execUnitId = wf->execUnitId;
+ gpuDynInst->latency.init(gpuDynInst->computeUnit());
+ gpuDynInst->latency.set(
+ gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ ConstVecOperandU64 data(gpuDynInst, extData.DATA0);
+
+ addr.read();
+ data.read();
+
+ calcAddr(gpuDynInst, addr);
+
+ for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+ if (gpuDynInst->exec_mask[lane]) {
+ (reinterpret_cast<VecElemU64*>(gpuDynInst->a_data))[lane]
+ = data[lane];
+ }
+ }
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+ void
+ Inst_DS__DS_ADD_U64::initiateAcc(GPUDynInstPtr gpuDynInst)
+ {
+ Addr offset0 = instData.OFFSET0;
+ Addr offset1 = instData.OFFSET1;
+ Addr offset = (offset1 << 8) | offset0;
+
+ initAtomicAccess<VecElemU64>(gpuDynInst, offset);
+ } // initiateAcc
+
+ void
+ Inst_DS__DS_ADD_U64::completeAcc(GPUDynInstPtr gpuDynInst)
+ {
+ } // completeAcc
// --- Inst_DS__DS_SUB_U64 class methods ---
Inst_DS__DS_SUB_U64::Inst_DS__DS_SUB_U64(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 05a0002..f8fc98b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33079,6 +33079,8 @@
}
} // getOperandSize
+ void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+ void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U64
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
Gerrit-Change-Number: 67075
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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