Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67201?usp=email )
Change subject: mem-ruby: add GPU cache bypass I->I transition
......................................................................
mem-ruby: add GPU cache bypass I->I transition
66d4a158 added support for AMD's GPU cache bypassing flags (GLC
for bypassing L1 caches, SLC for bypassing all caches). However,
it did not add a transition for the situation where the cache line
is currently I (Invalid). This commit adds this support, which
resolves an assert failure in Pannotia workloads when this situation
arises.
Change-Id: I59a62ce70c01dd8b73aacb733fb3d1d0dab2624b
---
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
1 file changed, 25 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
index 6a977c4..7e0ad4e 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
@@ -619,6 +619,15 @@
p_popMandatoryQueue;
}
+ // Transition to be called when a load request with GLC or SLC flag set
arrives
+ // at L1. Since the entry is invalid, there isn't anything to forward to
L2,
+ // so just issue read.
+ transition(I, LoadBypassEvict) {TagArrayRead, TagArrayWrite} {
+ uu_profileDataMiss;
+ n_issueRdBlk;
+ p_popMandatoryQueue;
+ }
+
transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
t_allocateTBE;
mru_updateMRU;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I59a62ce70c01dd8b73aacb733fb3d1d0dab2624b
Gerrit-Change-Number: 67201
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Sinclair <mattdsinclair.w...@gmail.com>
Gerrit-MessageType: newchange
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