Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67251?usp=email )
Change subject: arch-riscv: Check RISCV process run in matched CPU
......................................................................
arch-riscv: Check RISCV process run in matched CPU
The process should run correct CPU configuration instead of setting
RISCV flags by process
Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
---
M src/arch/riscv/process.cc
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae..e76933e 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@
Process::initState();
argsInit<uint64_t>(PageBytes);
- for (ContextID ctx: contextIds)
- system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+ for (ContextID ctx: contextIds) {
+ auto *tc = system->threads[ctx];
+ tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+ auto isa = dynamic_cast<ISA*>(tc->getIsaPtr());
+ panic_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits
mode");
+ }
}
void
@@ -114,9 +118,8 @@
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
- PCState pc = tc->pcState().as<PCState>();
- pc.rvType(RV32);
- tc->pcState(pc);
+ auto isa = dynamic_cast<ISA*>(tc->getIsaPtr());
+ panic_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits
mode");
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Gerrit-Change-Number: 67251
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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