Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64336?usp=email )
Change subject: arch-arm: Add interfaces to set and get SME vector length
......................................................................
arch-arm: Add interfaces to set and get SME vector length
We add interfaces which roughly mirror those already present for
manipulating the SVE vector lengths to set/get the SME vector length.
In the case of the SME vector length we also need to do some checking
to ensure that the vector length itself is aligned to a whole power of
two (one of the SME requirements).
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289
Change-Id: Ib89a4804466f5445adea6de8d65df512e366d618
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64336
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
6 files changed, 129 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index c315ecf..9fc4be0 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -67,6 +67,10 @@
sveLen = (safe_cast<ISA *>(params.isa)->
getCurSveVecLenInBitsAtReset() >> 7) - 1;
+ // Initialize SME vector length
+ smeLen = (safe_cast<ISA *>(params.isa)
+ ->getCurSmeVecLenInBitsAtReset() >> 7) - 1;
+
if (dvmEnabled) {
warn_once(
"DVM Ops instructions are micro-architecturally "
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 8e486a3..8369093 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -85,6 +85,12 @@
*/
int sveLen;
+ /**
+ * SME vector length, encoded in the same format as the SMCR_EL<x>.LEN
+ * bitfields.
+ */
+ int smeLen;
+
enums::DecoderFlavor decoderFlavor;
/// A cache of decoded instruction objects.
@@ -158,6 +164,12 @@
{
sveLen = len;
}
+
+ void
+ setSmeLen(uint8_t len)
+ {
+ smeLen = len;
+ }
};
} // namespace ArmISA
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index c07fb39..446f2af 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1233,5 +1233,13 @@
return isa->getCurSveVecLenInBits();
}
+unsigned
+ArmStaticInst::getCurSmeVecLenInBits(ThreadContext *tc)
+{
+ auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
+ return isa->getCurSmeVecLenInBits();
+}
+
+
} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index fa58f98..3b67e6b 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -583,6 +583,21 @@
return getCurSveVecLenInBits(tc) / (8 * sizeof(T));
}
+ static unsigned getCurSmeVecLenInBits(ThreadContext *tc);
+
+ static unsigned
+ getCurSmeVecLenInQWords(ThreadContext *tc)
+ {
+ return getCurSmeVecLenInBits(tc) >> 6;
+ }
+
+ template<typename T>
+ static unsigned
+ getCurSmeVecLen(ThreadContext *tc)
+ {
+ return getCurSmeVecLenInBits(tc) / (8 * sizeof(T));
+ }
+
inline Fault
undefined(bool disabled=false) const
{
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 78a1f4f..aec8243 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1162,6 +1162,8 @@
tc->getDecoderPtr()->as<Decoder>().setSveLen(
(getCurSveVecLenInBits() >> 7) - 1);
+ tc->getDecoderPtr()->as<Decoder>().setSmeLen(
+ (getCurSmeVecLenInBits() >> 7) - 1);
// Follow slightly different semantics if a CheckerCPU object
// is connected
@@ -2069,11 +2071,11 @@
case MISCREG_SMCR_EL2:
case MISCREG_SMCR_EL1:
// Set the value here as we need to update the regs before
- // reading them back in getCurSmeVecLenInBits (not
- // implemented yet) to avoid setting stale vector lengths in
- // the decoder.
+ // reading them back in getCurSmeVecLenInBits to avoid
+ // setting stale vector lengths in the decoder.
setMiscRegNoEffect(idx, newVal);
- // TODO: set the SME vector length
+ tc->getDecoderPtr()->as<Decoder>().setSmeLen(
+ (getCurSmeVecLenInBits() >> 7) - 1);
return;
}
setMiscRegNoEffect(idx, newVal);
@@ -2161,6 +2163,13 @@
unsigned
ISA::getCurSveVecLenInBits() const
{
+ SVCR svcr = miscRegs[MISCREG_SVCR];
+ // If we are in Streaming Mode, we should return the Streaming Mode
vector
+ // length instead.
+ if (svcr.sm) {
+ return getCurSmeVecLenInBits();
+ }
+
if (!FullSystem) {
return sveVL * 128;
}
@@ -2202,6 +2211,56 @@
return (len + 1) * 128;
}
+unsigned
+ISA::getCurSmeVecLenInBits() const
+{
+ if (!FullSystem) {
+ return smeVL * 128;
+ }
+
+ panic_if(!tc,
+ "A ThreadContext is needed to determine the SME vector
length "
+ "in full-system mode");
+
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+
+ unsigned len = 0;
+
+ if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
+ len = static_cast<SMCR>(miscRegs[MISCREG_SMCR_EL1]).len;
+ }
+
+ if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
+ len = static_cast<SMCR>(miscRegs[MISCREG_SMCR_EL2]).len;
+ } else if (release->has(ArmExtension::VIRTUALIZATION) && !isSecure(tc)
&&
+ (el == EL0 || el == EL1)) {
+ len = std::min(
+ len,
+ static_cast<unsigned>(
+ static_cast<SMCR>(miscRegs[MISCREG_SMCR_EL2]).len));
+ }
+
+ if (el == EL3) {
+ len = static_cast<SMCR>(miscRegs[MISCREG_SMCR_EL3]).len;
+ } else if (release->has(ArmExtension::SECURITY)) {
+ len = std::min(
+ len,
+ static_cast<unsigned>(
+ static_cast<SMCR>(miscRegs[MISCREG_SMCR_EL3]).len));
+ }
+
+ len = std::min(len, smeVL - 1);
+
+ // len + 1 must be a power of 2! Round down to the nearest whole power
of
+ // two.
+ static const unsigned LUT[16] = {0, 1, 1, 3, 3, 3, 3, 7,
+ 7, 7, 7, 7, 7, 7, 7, 15};
+ len = LUT[len];
+
+ return (len + 1) * 128;
+}
+
void
ISA::serialize(CheckpointOut &cp) const
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index bc0ab76..512799f 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -367,6 +367,10 @@
unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *
128; }
+ unsigned getCurSmeVecLenInBits() const;
+
+ unsigned getCurSmeVecLenInBitsAtReset() const { return smeVL *
128; }
+
template <typename Elem>
static void
zeroSveVecRegUpperPart(Elem *v, unsigned eCount)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib89a4804466f5445adea6de8d65df512e366d618
Gerrit-Change-Number: 64336
Gerrit-PatchSet: 7
Gerrit-Owner: Sascha Bischoff <sascha.bisch...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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