轩胡 has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/67294?usp=email )

Change subject: arch-riscv: Add risc-v vector ext v1.0 almost-complete support
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arch-riscv: Add risc-v vector ext v1.0 almost-complete support

* About 95% of the V extension commands have been implemented
* On Atomic/Timing Simple CPUs, all insts implemented has passed tests
* Almost every microop uses 4 source and 1 dest registers at most
* Move risc-v bitfields defined in bitfields.hh to bitfield.isa
* TODOs
  * More vector extension insts
    * Vector Compress Instruction
    * Fault-Only-First Loads
    * Vector Load/Store Segment Instructions
  * It is hard to implement these instructions using only microops
  without micro-arch modifications of CPU models(Minor and O3CPU)
  * For Atomic/Timing Simple CPUs, dummy implementations for these
  three kinds of instructions are needed

Change-Id: I84363164ca327151101e8a1c3d8441a66338c909
Co-authored-by: Xuan Hu <huxua...@bosc.ac.cn>
Co-authored-by: Yang Liu <numbk...@gmail.com>
Co-authored-by: Fan Yang <1209202...@qq.com>
Co-authored-by: Jerin Joy <j...@rivosinc.com>
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.hh
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/amo.cc
D src/arch/riscv/insts/bitfields.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/insts/unknown.hh
A src/arch/riscv/insts/vector.cc
A src/arch/riscv/insts/vector.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/formats.isa
A src/arch/riscv/isa/formats/vector_arith.isa
A src/arch/riscv/isa/formats/vector_conf.isa
A src/arch/riscv/isa/formats/vector_mem.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/main.isa
M src/arch/riscv/isa/operands.isa
A src/arch/riscv/isa/templates/templates.isa
A src/arch/riscv/isa/templates/vector_arith.isa
A src/arch/riscv/isa/templates/vector_mem.isa
M src/arch/riscv/regs/float.hh
M src/arch/riscv/regs/misc.hh
A src/arch/riscv/regs/vector.hh
M src/arch/riscv/types.hh
M src/arch/riscv/utility.hh
31 files changed, 9,370 insertions(+), 141 deletions(-)




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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I84363164ca327151101e8a1c3d8441a66338c909
Gerrit-Change-Number: 67294
Gerrit-PatchSet: 1
Gerrit-Owner: 轩胡 <huxuan0...@gmail.com>
Gerrit-MessageType: newchange
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