Melissa Jost has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67390?usp=email )
Change subject: cpu: Move execute stats from simple and minor to base
......................................................................
cpu: Move execute stats from simple and minor to base
Created stat group ExecuteCPUStats in BaseCPU and moved stats from the
simple and minor cpu models.
The stats moved from SimpleCPU are dcacheStallCycles,
icacheStallCycles, numCCRegReads, numCCRegWrites, numFpAluAccesses,
numFpRegReads, numFpRegWrites, numIntAluAccesses, numIntRegReads,
numIntRegWrites, numMemRefs, numMiscRegReads, numMiscRegWrites,
numVecAluAccesses, numVecPredRegReads, numVecPredRegWrites,
numVecRegReads, numVecRegWrites.
The stat moved from MinorCPU is numDiscardedOps.
Also, ccRegfileReads, ccRegfileWrites, fpRegfileReads, fpRegfileWrites,
intRegfileReads, intRegfileWrites, miscRegfileReads, miscRegfileWrites,
vecPredRegfileReads, vecPredRegfileWrites, vecRegfileReads,
and vecRegfileWrites are removed from cpu.hh and cpu.cc in O3CPU. The
corresponding stats in BaseCPU::ExecuteCPUStats are used instead.
Changed the getReg, getWritableReg, and setReg functions in the O3 CPU
object to take the thread ID as a parameter. This is because the stats
in base are stored in vectors that are indexed by thread ID.
Change-Id: I801c5ceb4c70b7b281127569f11c6ee98f614b27
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/stats.cc
M src/cpu/minor/stats.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/simple/base.cc
M src/cpu/simple/exec_context.hh
10 files changed, 220 insertions(+), 239 deletions(-)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 98453d7..7bdbfda 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -180,8 +180,10 @@
}
// create a stat group object for each thread on this core
fetchStats.reserve(numThreads);
+ executeStats.reserve(numThreads);
for (int i = 0; i < numThreads; i++) {
fetchStats.emplace_back(new FetchCPUStats(this, i));
+ executeStats.emplace_back(new ExecuteCPUStats(this, i));
}
}
@@ -799,4 +801,78 @@
}
+// means it is incremented in a vector indexing and not directly
+BaseCPU::
+ExecuteCPUStats::ExecuteCPUStats(statistics::Group *parent, int thread_id)
+ : statistics::Group(parent, csprintf("executeStats%i",
thread_id).c_str()),
+ ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
+ "DCache total stall cycles"),
+ ADD_STAT(numCCRegReads, statistics::units::Count::get(),
+ "Number of times the CC registers were read"),
+ ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
+ "Number of times the CC registers were written"),
+ ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
+ "Number of float alu accesses"),
+ ADD_STAT(numFpRegReads, statistics::units::Count::get(),
+ "Number of times the floating registers were read"),
+ ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
+ "Number of times the floating registers were written"),
+ ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
+ "Number of integer alu accesses"),
+ ADD_STAT(numIntRegReads, statistics::units::Count::get(),
+ "Number of times the integer registers were read"),
+ ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
+ "Number of times the integer registers were written"),
+ ADD_STAT(numMemRefs, statistics::units::Count::get(),
+ "Number of memory refs"),
+ ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
+ "Number of times the Misc registers were read"),
+ ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
+ "Number of times the Misc registers were written"),
+ ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
+ "Number of vector alu accesses"),
+ ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
+ "Number of times the predicate registers were read"),
+ ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
+ "Number of times the predicate registers were written"),
+ ADD_STAT(numVecRegReads, statistics::units::Count::get(),
+ "Number of times the vector registers were read"),
+ ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
+ "Number of times the vector registers were written"),
+ ADD_STAT(numDiscardedOps, statistics::units::Count::get(),
+ "Number of ops (including micro ops) which were discarded
before "
+ "commit")
+{
+ dcacheStallCycles
+ .prereq(dcacheStallCycles);
+ numCCRegReads
+ .prereq(numCCRegReads)
+ .flags(statistics::nozero);
+ numCCRegWrites
+ .prereq(numCCRegWrites)
+ .flags(statistics::nozero);
+ numFpAluAccesses
+ .prereq(numFpAluAccesses);
+ numFpRegReads
+ .prereq(numFpRegReads);
+ numIntAluAccesses
+ .prereq(numIntAluAccesses);
+ numIntRegReads
+ .prereq(numIntRegReads);
+ numIntRegWrites
+ .prereq(numIntRegWrites);
+ numMiscRegReads
+ .prereq(numMiscRegReads);
+ numMiscRegWrites
+ .prereq(numMiscRegWrites);
+ numVecPredRegReads
+ .prereq(numVecPredRegReads);
+ numVecPredRegWrites
+ .prereq(numVecPredRegWrites);
+ numVecRegReads
+ .prereq(numVecRegReads);
+ numVecRegWrites
+ .prereq(numVecRegWrites);
+}
+
} // namespace gem5
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 8d185e4..ea77ac5 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -674,7 +674,55 @@
};
+ struct ExecuteCPUStats: public statistics::Group
+ {
+ ExecuteCPUStats(statistics::Group *parent, int thread_id);
+
+ /* Number of cycles stalled for D-cache responses */
+ statistics::Scalar dcacheStallCycles;
+
+ /* Number of condition code register file accesses */
+ statistics::Scalar numCCRegReads;
+ statistics::Scalar numCCRegWrites;
+
+ /* number of float alu accesses */
+ statistics::Scalar numFpAluAccesses;
+
+ /* Number of float register file accesses */
+ statistics::Scalar numFpRegReads;
+ statistics::Scalar numFpRegWrites;
+
+ /* Number of integer alu accesses */
+ statistics::Scalar numIntAluAccesses;
+
+ /* Number of integer register file accesses */
+ statistics::Scalar numIntRegReads;
+ statistics::Scalar numIntRegWrites;
+
+ /* number of simulated memory references */
+ statistics::Scalar numMemRefs;
+
+ /* Number of misc register file accesses */
+ statistics::Scalar numMiscRegReads;
+ statistics::Scalar numMiscRegWrites;
+
+ /* Number of vector alu accesses */
+ statistics::Scalar numVecAluAccesses;
+
+ /* Number of predicate register file accesses */
+ mutable statistics::Scalar numVecPredRegReads;
+ statistics::Scalar numVecPredRegWrites;
+
+ /* Number of vector register file accesses */
+ mutable statistics::Scalar numVecRegReads;
+ statistics::Scalar numVecRegWrites;
+
+ /* Number of ops discarded before committing */
+ statistics::Scalar numDiscardedOps;
+ };
+
std::vector<std::unique_ptr<FetchCPUStats>> fetchStats;
+ std::vector<std::unique_ptr<ExecuteCPUStats>> executeStats;
};
} // namespace gem5
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 323ae29..d657de5 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -1368,7 +1368,7 @@
*inst, ex_info.streamSeqNum);
if (fault == NoFault)
- cpu.stats.numDiscardedOps++;
+ cpu.executeStats[thread_id]->numDiscardedOps++;
}
/* Mark the mem inst as being in the LSQ */
diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc
index e9ca562..10e7573 100644
--- a/src/cpu/minor/stats.cc
+++ b/src/cpu/minor/stats.cc
@@ -49,9 +49,6 @@
"Number of instructions committed"),
ADD_STAT(numOps, statistics::units::Count::get(),
"Number of ops (including micro ops) committed"),
- ADD_STAT(numDiscardedOps, statistics::units::Count::get(),
- "Number of ops (including micro ops) which were discarded
before "
- "commit"),
ADD_STAT(quiesceCycles, statistics::units::Cycle::get(),
"Total number of cycles that CPU has spent quiesced or
waiting "
"for an interrupt"),
diff --git a/src/cpu/minor/stats.hh b/src/cpu/minor/stats.hh
index 524d20f..e5d0186 100644
--- a/src/cpu/minor/stats.hh
+++ b/src/cpu/minor/stats.hh
@@ -65,9 +65,6 @@
/** Number of simulated insts and microops */
statistics::Scalar numOps;
- /** Number of ops discarded before committing */
- statistics::Scalar numDiscardedOps;
-
/** Number of cycles in quiescent state */
statistics::Scalar quiesceCycles;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index d2bacaa..90df3b3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -344,31 +344,7 @@
"IPC: Instructions Per Cycle"),
ADD_STAT(totalIpc, statistics::units::Rate<
statistics::units::Count,
statistics::units::Cycle>::get(),
- "IPC: Total IPC of All Threads"),
- ADD_STAT(intRegfileReads, statistics::units::Count::get(),
- "Number of integer regfile reads"),
- ADD_STAT(intRegfileWrites, statistics::units::Count::get(),
- "Number of integer regfile writes"),
- ADD_STAT(fpRegfileReads, statistics::units::Count::get(),
- "Number of floating regfile reads"),
- ADD_STAT(fpRegfileWrites, statistics::units::Count::get(),
- "Number of floating regfile writes"),
- ADD_STAT(vecRegfileReads, statistics::units::Count::get(),
- "number of vector regfile reads"),
- ADD_STAT(vecRegfileWrites, statistics::units::Count::get(),
- "number of vector regfile writes"),
- ADD_STAT(vecPredRegfileReads, statistics::units::Count::get(),
- "number of predicate regfile reads"),
- ADD_STAT(vecPredRegfileWrites, statistics::units::Count::get(),
- "number of predicate regfile writes"),
- ADD_STAT(ccRegfileReads, statistics::units::Count::get(),
- "number of cc regfile reads"),
- ADD_STAT(ccRegfileWrites, statistics::units::Count::get(),
- "number of cc regfile writes"),
- ADD_STAT(miscRegfileReads, statistics::units::Count::get(),
- "number of misc regfile reads"),
- ADD_STAT(miscRegfileWrites, statistics::units::Count::get(),
- "number of misc regfile writes")
+ "IPC: Total IPC of All Threads")
{
// Register any of the O3CPU's stats here.
timesIdled
@@ -407,42 +383,6 @@
totalIpc
.precision(6);
totalIpc = sum(committedInsts) / cpu->baseStats.numCycles;
-
- intRegfileReads
- .prereq(intRegfileReads);
-
- intRegfileWrites
- .prereq(intRegfileWrites);
-
- fpRegfileReads
- .prereq(fpRegfileReads);
-
- fpRegfileWrites
- .prereq(fpRegfileWrites);
-
- vecRegfileReads
- .prereq(vecRegfileReads);
-
- vecRegfileWrites
- .prereq(vecRegfileWrites);
-
- vecPredRegfileReads
- .prereq(vecPredRegfileReads);
-
- vecPredRegfileWrites
- .prereq(vecPredRegfileWrites);
-
- ccRegfileReads
- .prereq(ccRegfileReads);
-
- ccRegfileWrites
- .prereq(ccRegfileWrites);
-
- miscRegfileReads
- .prereq(miscRegfileReads);
-
- miscRegfileWrites
- .prereq(miscRegfileWrites);
}
void
@@ -1019,7 +959,7 @@
RegVal
CPU::readMiscReg(int misc_reg, ThreadID tid)
{
- cpuStats.miscRegfileReads++;
+ executeStats[tid]->numMiscRegReads++;
return isa[tid]->readMiscReg(misc_reg);
}
@@ -1032,29 +972,29 @@
void
CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
- cpuStats.miscRegfileWrites++;
+ executeStats[tid]->numMiscRegWrites++;
isa[tid]->setMiscReg(misc_reg, val);
}
RegVal
-CPU::getReg(PhysRegIdPtr phys_reg)
+CPU::getReg(PhysRegIdPtr phys_reg, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
- cpuStats.intRegfileReads++;
+ executeStats[tid]->numIntRegReads++;
break;
case FloatRegClass:
- cpuStats.fpRegfileReads++;
+ executeStats[tid]->numFpRegReads++;
break;
case CCRegClass:
- cpuStats.ccRegfileReads++;
+ executeStats[tid]->numCCRegReads++;
break;
case VecRegClass:
case VecElemClass:
- cpuStats.vecRegfileReads++;
+ executeStats[tid]->numVecRegReads++;
break;
case VecPredRegClass:
- cpuStats.vecPredRegfileReads++;
+ executeStats[tid]->numVecPredRegReads++;
break;
default:
break;
@@ -1063,24 +1003,24 @@
}
void
-CPU::getReg(PhysRegIdPtr phys_reg, void *val)
+CPU::getReg(PhysRegIdPtr phys_reg, void *val, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
- cpuStats.intRegfileReads++;
+ executeStats[tid]->numIntRegReads++;
break;
case FloatRegClass:
- cpuStats.fpRegfileReads++;
+ executeStats[tid]->numFpRegReads++;
break;
case CCRegClass:
- cpuStats.ccRegfileReads++;
+ executeStats[tid]->numCCRegReads++;
break;
case VecRegClass:
case VecElemClass:
- cpuStats.vecRegfileReads++;
+ executeStats[tid]->numVecRegReads++;
break;
case VecPredRegClass:
- cpuStats.vecPredRegfileReads++;
+ executeStats[tid]->numVecPredRegReads++;
break;
default:
break;
@@ -1089,14 +1029,14 @@
}
void *
-CPU::getWritableReg(PhysRegIdPtr phys_reg)
+CPU::getWritableReg(PhysRegIdPtr phys_reg, ThreadID tid)
{
switch (phys_reg->classValue()) {
case VecRegClass:
- cpuStats.vecRegfileReads++;
+ executeStats[tid]->numVecRegReads++;
break;
case VecPredRegClass:
- cpuStats.vecPredRegfileReads++;
+ executeStats[tid]->numVecPredRegReads++;
break;
default:
break;
@@ -1105,24 +1045,24 @@
}
void
-CPU::setReg(PhysRegIdPtr phys_reg, RegVal val)
+CPU::setReg(PhysRegIdPtr phys_reg, RegVal val, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
- cpuStats.intRegfileWrites++;
+ executeStats[tid]->numIntRegWrites++;
break;
case FloatRegClass:
- cpuStats.fpRegfileWrites++;
+ executeStats[tid]->numFpRegWrites++;
break;
case CCRegClass:
- cpuStats.ccRegfileWrites++;
+ executeStats[tid]->numCCRegWrites++;
break;
case VecRegClass:
case VecElemClass:
- cpuStats.vecRegfileWrites++;
+ executeStats[tid]->numVecRegWrites++;
break;
case VecPredRegClass:
- cpuStats.vecPredRegfileWrites++;
+ executeStats[tid]->numVecPredRegWrites++;
break;
default:
break;
@@ -1131,24 +1071,24 @@
}
void
-CPU::setReg(PhysRegIdPtr phys_reg, const void *val)
+CPU::setReg(PhysRegIdPtr phys_reg, const void *val, ThreadID tid)
{
switch (phys_reg->classValue()) {
case IntRegClass:
- cpuStats.intRegfileWrites++;
+ executeStats[tid]->numIntRegWrites++;
break;
case FloatRegClass:
- cpuStats.fpRegfileWrites++;
+ executeStats[tid]->numFpRegWrites++;
break;
case CCRegClass:
- cpuStats.ccRegfileWrites++;
+ executeStats[tid]->numCCRegWrites++;
break;
case VecRegClass:
case VecElemClass:
- cpuStats.vecRegfileWrites++;
+ executeStats[tid]->numVecRegWrites++;
break;
case VecPredRegClass:
- cpuStats.vecPredRegfileWrites++;
+ executeStats[tid]->numVecPredRegWrites++;
break;
default:
break;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 08a1312..0777529 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -310,12 +310,12 @@
*/
void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
- RegVal getReg(PhysRegIdPtr phys_reg);
- void getReg(PhysRegIdPtr phys_reg, void *val);
- void *getWritableReg(PhysRegIdPtr phys_reg);
+ RegVal getReg(PhysRegIdPtr phys_reg, ThreadID tid);
+ void getReg(PhysRegIdPtr phys_reg, void *val, ThreadID tid);
+ void *getWritableReg(PhysRegIdPtr phys_reg, ThreadID tid);
- void setReg(PhysRegIdPtr phys_reg, RegVal val);
- void setReg(PhysRegIdPtr phys_reg, const void *val);
+ void setReg(PhysRegIdPtr phys_reg, RegVal val, ThreadID tid);
+ void setReg(PhysRegIdPtr phys_reg, const void *val, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
@@ -595,24 +595,6 @@
/** Stat for the total IPC. */
statistics::Formula totalIpc;
- //number of integer register file accesses
- statistics::Scalar intRegfileReads;
- statistics::Scalar intRegfileWrites;
- //number of float register file accesses
- statistics::Scalar fpRegfileReads;
- statistics::Scalar fpRegfileWrites;
- //number of vector register file accesses
- mutable statistics::Scalar vecRegfileReads;
- statistics::Scalar vecRegfileWrites;
- //number of predicate register file accesses
- mutable statistics::Scalar vecPredRegfileReads;
- statistics::Scalar vecPredRegfileWrites;
- //number of CC register file accesses
- statistics::Scalar ccRegfileReads;
- statistics::Scalar ccRegfileWrites;
- //number of misc
- statistics::Scalar miscRegfileReads;
- statistics::Scalar miscRegfileWrites;
} cpuStats;
public:
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index ab165bb..ce39b42 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1085,10 +1085,10 @@
if (bytes == sizeof(RegVal)) {
setRegOperand(staticInst.get(), idx,
- cpu->getReg(prev_phys_reg));
+ cpu->getReg(prev_phys_reg, threadNumber));
} else {
uint8_t val[original_dest_reg.regClass().regBytes()];
- cpu->getReg(prev_phys_reg, val);
+ cpu->getReg(prev_phys_reg, val, threadNumber);
setRegOperand(staticInst.get(), idx, val);
}
}
@@ -1115,7 +1115,7 @@
const PhysRegIdPtr reg = renamedSrcIdx(idx);
if (reg->is(InvalidRegClass))
return 0;
- return cpu->getReg(reg);
+ return cpu->getReg(reg, threadNumber);
}
void
@@ -1124,13 +1124,13 @@
const PhysRegIdPtr reg = renamedSrcIdx(idx);
if (reg->is(InvalidRegClass))
return;
- cpu->getReg(reg, val);
+ cpu->getReg(reg, val, threadNumber);
}
void *
getWritableRegOperand(const StaticInst *si, int idx) override
{
- return cpu->getWritableReg(renamedDestIdx(idx));
+ return cpu->getWritableReg(renamedDestIdx(idx), threadNumber);
}
/** @todo: Make results into arrays so they can handle multiple dest
@@ -1142,7 +1142,7 @@
const PhysRegIdPtr reg = renamedDestIdx(idx);
if (reg->is(InvalidRegClass))
return;
- cpu->setReg(reg, val);
+ cpu->setReg(reg, val, threadNumber);
setResult(reg->regClass(), val);
}
@@ -1152,7 +1152,7 @@
const PhysRegIdPtr reg = renamedDestIdx(idx);
if (reg->is(InvalidRegClass))
return;
- cpu->setReg(reg, val);
+ cpu->setReg(reg, val, threadNumber);
setResult(reg->regClass(), val);
}
};
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b2a11fd..c8d9aee 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -388,7 +388,7 @@
Addr instAddr = threadContexts[curThread]->pcState().instAddr();
if (curStaticInst->isMemRef()) {
- t_info.execContextStats.numMemRefs++;
+ executeStats[t_info.thread->threadId()]->numMemRefs++;
}
if (curStaticInst->isLoad()) {
@@ -402,19 +402,19 @@
/* Power model statistics */
//integer alu accesses
if (curStaticInst->isInteger()){
- t_info.execContextStats.numIntAluAccesses++;
+ executeStats[t_info.thread->threadId()]->numIntAluAccesses++;
t_info.execContextStats.numIntInsts++;
}
//float alu accesses
if (curStaticInst->isFloating()){
- t_info.execContextStats.numFpAluAccesses++;
+ executeStats[t_info.thread->threadId()]->numFpAluAccesses++;
t_info.execContextStats.numFpInsts++;
}
//vector alu accesses
if (curStaticInst->isVector()){
- t_info.execContextStats.numVecAluAccesses++;
+ executeStats[t_info.thread->threadId()]->numVecAluAccesses++;
t_info.execContextStats.numVecInsts++;
}
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 65b902e..00efd85 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -90,12 +90,6 @@
"Number of instructions committed"),
ADD_STAT(numOps, statistics::units::Count::get(),
"Number of ops (including micro ops) committed"),
- ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
- "Number of integer alu accesses"),
- ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
- "Number of float alu accesses"),
- ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
- "Number of vector alu accesses"),
ADD_STAT(numMatAluAccesses, statistics::units::Count::get(),
"Number of matrix alu accesses"),
ADD_STAT(numCallsReturns, statistics::units::Count::get(),
@@ -110,32 +104,6 @@
"Number of vector instructions"),
ADD_STAT(numMatInsts, statistics::units::Count::get(),
"Number of matrix instructions"),
- ADD_STAT(numIntRegReads, statistics::units::Count::get(),
- "Number of times the integer registers were read"),
- ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
- "Number of times the integer registers were
written"),
- ADD_STAT(numFpRegReads, statistics::units::Count::get(),
- "Number of times the floating registers were read"),
- ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
- "Number of times the floating registers were
written"),
- ADD_STAT(numVecRegReads, statistics::units::Count::get(),
- "Number of times the vector registers were read"),
- ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
- "Number of times the vector registers were
written"),
- ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
- "Number of times the predicate registers were
read"),
- ADD_STAT(numVecPredRegWrites,
statistics::units::Count::get(),
- "Number of times the predicate registers were
written"),
- ADD_STAT(numCCRegReads, statistics::units::Count::get(),
- "Number of times the CC registers were read"),
- ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
- "Number of times the CC registers were written"),
- ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
- "Number of times the Misc registers were read"),
- ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
- "Number of times the Misc registers were written"),
- ADD_STAT(numMemRefs, statistics::units::Count::get(),
- "Number of memory refs"),
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
"Number of load instructions"),
ADD_STAT(numStoreInsts, statistics::units::Count::get(),
@@ -148,12 +116,6 @@
"Percentage of non-idle cycles"),
ADD_STAT(idleFraction, statistics::units::Ratio::get(),
"Percentage of idle cycles"),
- ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
- "ICache total stall cycles"),
- ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
- "DCache total stall cycles"),
- ADD_STAT(numBranches, statistics::units::Count::get(),
- "Number of branches fetched"),
ADD_STAT(numPredictedBranches,
statistics::units::Count::get(),
"Number of branches predicted as taken"),
ADD_STAT(numBranchMispred, statistics::units::Count::get(),
@@ -161,36 +123,25 @@
ADD_STAT(statExecutedInstType,
statistics::units::Count::get(),
"Class of executed instruction."),
numRegReads{
- &numIntRegReads,
- &numFpRegReads,
- &numVecRegReads,
- &numVecRegReads,
- &numVecPredRegReads,
- &numMatRegReads,
- &numCCRegReads
+ &(cpu->executeStats[thread->threadId()]->numIntRegReads),
+ &(cpu->executeStats[thread->threadId()]->numFpRegReads),
+ &(cpu->executeStats[thread->threadId()]->numVecRegReads),
+ &(cpu->executeStats[thread->threadId()]->numVecRegReads),
+
&(cpu->executeStats[thread->threadId()]->numVecPredRegReads),
+ &(cpu->executeStats[thread->threadId()]->numCCRegReads),
+ &numMatRegReads
},
numRegWrites{
- &numIntRegWrites,
- &numFpRegWrites,
- &numVecRegWrites,
- &numVecRegWrites,
- &numVecPredRegWrites,
- &numMatRegWrites,
- &numCCRegWrites
+
&(cpu->executeStats[thread->threadId()]->numIntRegWrites),
+ &(cpu->executeStats[thread->threadId()]->numFpRegWrites),
+
&(cpu->executeStats[thread->threadId()]->numVecRegWrites),
+
&(cpu->executeStats[thread->threadId()]->numVecRegWrites),
+ &(cpu->executeStats[thread->threadId()]
+ ->numVecPredRegWrites),
+ &(cpu->executeStats[thread->threadId()]->numCCRegWrites),
+ &numMatRegWrites
}
{
- numCCRegReads
- .flags(statistics::nozero);
-
- numCCRegWrites
- .flags(statistics::nozero);
-
- icacheStallCycles
- .prereq(icacheStallCycles);
-
- dcacheStallCycles
- .prereq(dcacheStallCycles);
-
statExecutedInstType
.init(enums::Num_OpClass)
.flags(statistics::total | statistics::pdf |
statistics::dist);
@@ -214,15 +165,6 @@
statistics::Scalar numInsts;
statistics::Scalar numOps;
- // Number of integer alu accesses
- statistics::Scalar numIntAluAccesses;
-
- // Number of float alu accesses
- statistics::Scalar numFpAluAccesses;
-
- // Number of vector alu accesses
- statistics::Scalar numVecAluAccesses;
-
// Number of matrix alu accesses
statistics::Scalar numMatAluAccesses;
@@ -244,36 +186,11 @@
// Number of matrix instructions
statistics::Scalar numMatInsts;
- // Number of integer register file accesses
- statistics::Scalar numIntRegReads;
- statistics::Scalar numIntRegWrites;
-
- // Number of float register file accesses
- statistics::Scalar numFpRegReads;
- statistics::Scalar numFpRegWrites;
-
- // Number of vector register file accesses
- mutable statistics::Scalar numVecRegReads;
- statistics::Scalar numVecRegWrites;
-
- // Number of predicate register file accesses
- mutable statistics::Scalar numVecPredRegReads;
- statistics::Scalar numVecPredRegWrites;
-
// Number of matrix register file accesses
mutable statistics::Scalar numMatRegReads;
statistics::Scalar numMatRegWrites;
- // Number of condition code register file accesses
- statistics::Scalar numCCRegReads;
- statistics::Scalar numCCRegWrites;
-
- // Number of misc register file accesses
- statistics::Scalar numMiscRegReads;
- statistics::Scalar numMiscRegWrites;
-
// Number of simulated memory references
- statistics::Scalar numMemRefs;
statistics::Scalar numLoadInsts;
statistics::Scalar numStoreInsts;
@@ -287,12 +204,6 @@
statistics::Average notIdleFraction;
statistics::Formula idleFraction;
- // Number of cycles stalled for I-cache responses
- statistics::Scalar icacheStallCycles;
-
- // Number of cycles stalled for D-cache responses
- statistics::Scalar dcacheStallCycles;
-
/// @{
/// Number of branches predicted as taken
statistics::Scalar numPredictedBranches;
@@ -363,7 +274,7 @@
RegVal
readMiscRegOperand(const StaticInst *si, int idx) override
{
- execContextStats.numMiscRegReads++;
+ cpu->executeStats[thread->threadId()]->numMiscRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.is(MiscRegClass));
return thread->readMiscReg(reg.index());
@@ -372,7 +283,7 @@
void
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
- execContextStats.numMiscRegWrites++;
+ cpu->executeStats[thread->threadId()]->numMiscRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.is(MiscRegClass));
thread->setMiscReg(reg.index(), val);
@@ -385,7 +296,7 @@
RegVal
readMiscReg(int misc_reg) override
{
- execContextStats.numMiscRegReads++;
+ cpu->executeStats[thread->threadId()]->numMiscRegReads++;
return thread->readMiscReg(misc_reg);
}
@@ -396,7 +307,7 @@
void
setMiscReg(int misc_reg, RegVal val) override
{
- execContextStats.numMiscRegWrites++;
+ cpu->executeStats[thread->threadId()]->numMiscRegWrites++;
thread->setMiscReg(misc_reg, val);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I801c5ceb4c70b7b281127569f11c6ee98f614b27
Gerrit-Change-Number: 67390
Gerrit-PatchSet: 1
Gerrit-Owner: Melissa Jost <melissakj...@gmail.com>
Gerrit-MessageType: newchange
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