Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67412?usp=email )
Change subject: arch-vega: Make VGPR-offset for global SGPR-base signed
......................................................................
arch-vega: Make VGPR-offset for global SGPR-base signed
The VGPR-offset used when SGPR-base addressing is used can be signed in
Vega. These are global instructions of the format:
`global_load_dword v0, v1, s[0:1]`. This is not explicitly stated in the
ISA manual however based on compiler output the offset can be negative.
This changeset assigns the offset to a signed 32-bit integer and the
compiler takes care of the signedness in the expression which calculates
the final address. This fixes a bad address calculation in a rocPRIM
unit test.
Change-Id: I271edfbb4c6344cb1a6a69a0fd3df58a6198d599
---
M src/arch/amdgpu/vega/insts/op_encodings.hh
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh
b/src/arch/amdgpu/vega/insts/op_encodings.hh
index 34f6040..1f52c75 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.hh
+++ b/src/arch/amdgpu/vega/insts/op_encodings.hh
@@ -1007,8 +1007,9 @@
// mask any upper bits from the vaddr.
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
+ ScalarRegI32 voffset = vaddr[lane] & 0xffffffff;
gpuDynInst->addr.at(lane) =
- saddr.rawData() + (vaddr[lane] & 0xffffffff) +
offset;
+ saddr.rawData() + voffset + offset;
}
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I271edfbb4c6344cb1a6a69a0fd3df58a6198d599
Gerrit-Change-Number: 67412
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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