chengyong zhong has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67717?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-riscv: Fix the CSR instruction behavior.
......................................................................
arch-riscv: Fix the CSR instruction behavior.
The RISC-V spec clarifies the CSR instruction operation, some of them
shall not read or write CSR by the hints of RD/RS1/uimm, but the
original version use the 'data != oldData' condition to determine
whether write or not, and always read CSR first.
See CSR instruction in spec:
Section 9.1 Page 56 of
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67717
Reviewed-by: Hoa Nguyen <hoangu...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 45 insertions(+), 7 deletions(-)
Approvals:
Hoa Nguyen: Looks good to me, approved
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index 5b0e8c2..afcfd7a 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -91,18 +91,33 @@
protected:
uint64_t csr;
uint64_t uimm;
+ bool read;
+ bool write;
/// Constructor
CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
- csr(FUNCT12), uimm(CSRIMM)
+ csr(FUNCT12), uimm(CSRIMM), read(true), write(true)
{
if (csr == CSR_SATP) {
flags[IsSquashAfter] = true;
}
+ if (strcmp(mnemonic, "csrrw") == 0 ||
+ strcmp(mnemonic, "csrrwi") == 0) {
+ if (RD == 0){
+ read = false;
+ }
+ } else if (strcmp(mnemonic, "csrrs") == 0 ||
+ strcmp(mnemonic, "csrrc") == 0 ||
+ strcmp(mnemonic, "csrrsi") == 0 ||
+ strcmp(mnemonic, "csrrci") == 0 ){
+ if (RS1 == 0) {
+ write = false;
+ }
+ }
}
- std::string generateDisassembly(
+ std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index bb500f5..1bd431a 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
%(op_decl)s;
%(op_rd)s;
- RegVal data, olddata;
+ RegVal data = 0, olddata = 0;
auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
if (pm < lowestAllowedMode) {
@@ -380,11 +380,13 @@
break;
}
- if (csr == CSR_FCSR) {
+ if (read) {
+ if (csr == CSR_FCSR) {
olddata = xc->readMiscReg(MISCREG_FFLAGS) |
- (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
- } else {
+ (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+ } else {
olddata = xc->readMiscReg(midx);
+ }
}
olddata = rvZext(olddata);
auto olddata_all = olddata;
@@ -396,7 +398,7 @@
%(code)s;
data &= maskVal;
- if (data != olddata) {
+ if (write) {
if (bits(csr, 11, 10) == 0x3) {
return std::make_shared<IllegalInstFault>(
csprintf("CSR %s is read-only\n", csrName),
machInst);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
Gerrit-Change-Number: 67717
Gerrit-PatchSet: 3
Gerrit-Owner: chengyong zhong <zhongc...@gmail.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: chengyong zhong <zhongc...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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