See <https://jenkins.gem5.org/job/nightly/559/display/redirect?page=changes>
Changes: [huxuan0307] ext: Update softfloat to 3d full version [gabe.black] base,cpu,dev,sim: Pull common logic into ListenSocket::listen(). [gabe.black] base: Make ListenSocket::listen(int port) protected. ------------------------------------------ [...truncated 1.63 MB...] [ CXX] ALL_MSI/cpu/o3/thread_state.cc -> .o [ TRACING] -> ALL_MSI/debug/CommitRate.cc [ CXX] ALL_MSI/debug/CommitRate.cc -> .o [ TRACING] -> ALL_MSI/debug/IEW.cc [ TRACING] -> ALL_MSI/debug/IQ.cc [ CXX] ALL_MSI/debug/IEW.cc -> .o [ TRACING] -> ALL_MSI/debug/LSQ.cc [ CXX] ALL_MSI/debug/IQ.cc -> .o [ CXX] ALL_MSI/debug/LSQ.cc -> .o [ TRACING] -> ALL_MSI/debug/LSQUnit.cc [ TRACING] -> ALL_MSI/debug/MemDepUnit.cc [ CXX] ALL_MSI/debug/LSQUnit.cc -> .o [ TRACING] -> ALL_MSI/debug/O3CPU.cc [ CXX] ALL_MSI/debug/MemDepUnit.cc -> .o [ CXX] ALL_MSI/debug/O3CPU.cc -> .o [ TRACING] -> ALL_MSI/debug/ROB.cc [ CXX] ALL_MSI/debug/ROB.cc -> .o [ TRACING] -> ALL_MSI/debug/Rename.cc [ TRACING] -> ALL_MSI/debug/Scoreboard.cc [ CXX] ALL_MSI/debug/Rename.cc -> .o [ TRACING] -> ALL_MSI/debug/StoreSet.cc [ CXX] ALL_MSI/debug/Scoreboard.cc -> .o [ TRACING] -> ALL_MSI/debug/Writeback.cc [ CXX] ALL_MSI/debug/StoreSet.cc -> .o [ CXX] ALL_MSI/debug/Writeback.cc -> .o [ TRACING] -> ALL_MSI/debug/O3CPUAll.cc [ TRACING] -> ALL_MSI/debug/O3CPUAll.hh [ CXX] ALL_MSI/cpu/o3/BaseO3Checker.py.cc -> .o [ CXX] ALL_MSI/debug/O3CPUAll.cc -> .o [SO Param] m5.objects.BaseO3Checker, BaseO3Checker -> ALL_MSI/python/_m5/param_BaseO3Checker.cc [ CXX] ALL_MSI/cpu/o3/checker.cc -> .o [ CXX] ALL_MSI/cpu/o3/O3CPU.py.cc -> .o [ CXX] ALL_MSI/cpu/o3/O3Checker.py.cc -> .o [ CXX] ALL_MSI/cpu/o3/probe/SimpleTrace.py.cc -> .o [SO Param] m5.objects.SimpleTrace, SimpleTrace -> ALL_MSI/python/_m5/param_SimpleTrace.cc [SO Param] m5.objects.BaseO3Checker, BaseO3Checker -> ALL_MSI/params/BaseO3Checker.hh [ TRACING] -> ALL_MSI/debug/SimpleTrace.hh [SO Param] m5.objects.SimpleTrace, SimpleTrace -> ALL_MSI/params/SimpleTrace.hh [ TRACING] -> ALL_MSI/debug/SimpleTrace.cc [ CXX] ALL_MSI/cpu/o3/probe/ElasticTrace.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_BaseO3Checker.cc -> .o [ CXX] ALL_MSI/debug/SimpleTrace.cc -> .o [SO Param] m5.objects.ElasticTrace, ElasticTrace -> ALL_MSI/python/_m5/param_ElasticTrace.cc [ CXX] ALL_MSI/cpu/o3/probe/simple_trace.cc -> .o [SO Param] m5.objects.ElasticTrace, ElasticTrace -> ALL_MSI/params/ElasticTrace.hh [ PROTOC] ALL_MSI/proto/inst_dep_record.proto -> ALL_MSI/proto/inst_dep_record.pb.cc, ALL_MSI/proto/inst_dep_record.pb.h [ PROTOC] ALL_MSI/proto/packet.proto -> ALL_MSI/proto/packet.pb.cc, ALL_MSI/proto/packet.pb.h [ CXX] ALL_MSI/python/_m5/param_SimpleTrace.cc -> .o [ TRACING] -> ALL_MSI/debug/ElasticTrace.hh [ TRACING] -> ALL_MSI/debug/ElasticTrace.cc [ CXX] ALL_MSI/cpu/trace/TraceCPU.py.cc -> .o [SO Param] m5.objects.TraceCPU, TraceCPU -> ALL_MSI/python/_m5/param_TraceCPU.cc [ CXX] ALL_MSI/debug/ElasticTrace.cc -> .o [ CXX] ALL_MSI/cpu/o3/probe/elastic_trace.cc -> .o [SO Param] m5.objects.TraceCPU, TraceCPU -> ALL_MSI/params/TraceCPU.hh [ TRACING] -> ALL_MSI/debug/TraceCPUData.hh [ TRACING] -> ALL_MSI/debug/TraceCPUInst.hh [ CXX] ALL_MSI/python/_m5/param_ElasticTrace.cc -> .o [ CXX] ALL_MSI/python/_m5/param_TraceCPU.cc -> .o [ CXX] ALL_MSI/cpu/trace/trace_cpu.cc -> .o [ TRACING] -> ALL_MSI/debug/TraceCPUData.cc [ CXX] ALL_MSI/debug/TraceCPUData.cc -> .o [ TRACING] -> ALL_MSI/debug/TraceCPUInst.cc [ CXX] ALL_MSI/debug/TraceCPUInst.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/RubyDirectedTester.py.cc -> .o [SO Param] m5.objects.RubyDirectedTester, DirectedGenerator -> ALL_MSI/python/_m5/param_DirectedGenerator.cc [SO Param] m5.objects.RubyDirectedTester, SeriesRequestGenerator -> ALL_MSI/python/_m5/param_SeriesRequestGenerator.cc [SO Param] m5.objects.RubyDirectedTester, InvalidateGenerator -> ALL_MSI/python/_m5/param_InvalidateGenerator.cc [SO Param] m5.objects.RubyDirectedTester, RubyDirectedTester -> ALL_MSI/python/_m5/param_RubyDirectedTester.cc [SO Param] m5.objects.RubyDirectedTester, SeriesRequestGenerator -> ALL_MSI/params/SeriesRequestGenerator.hh [SO Param] m5.objects.RubyDirectedTester, DirectedGenerator -> ALL_MSI/params/DirectedGenerator.hh [SO Param] m5.objects.RubyDirectedTester, RubyDirectedTester -> ALL_MSI/params/RubyDirectedTester.hh [SO Param] m5.objects.RubyDirectedTester, InvalidateGenerator -> ALL_MSI/params/InvalidateGenerator.hh [ TRACING] -> ALL_MSI/debug/DirectedTest.hh [ TRACING] -> ALL_MSI/debug/DirectedTest.cc [ CXX] ALL_MSI/cpu/testers/memtest/MemTest.py.cc -> .o [ CXX] ALL_MSI/debug/DirectedTest.cc -> .o [SO Param] m5.objects.MemTest, MemTest -> ALL_MSI/python/_m5/param_MemTest.cc [ TRACING] -> ALL_MSI/debug/MemTest.hh [SO Param] m5.objects.MemTest, MemTest -> ALL_MSI/params/MemTest.hh [ CXX] ALL_MSI/python/_m5/param_SeriesRequestGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_InvalidateGenerator.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/InvalidateGenerator.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/SeriesRequestGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_DirectedGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MemTest.cc -> .o [ CXX] ALL_MSI/cpu/testers/memtest/memtest.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/DirectedGenerator.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/RubyDirectedTester.cc -> .o [ CXX] ALL_MSI/python/_m5/param_RubyDirectedTester.cc -> .o [ TRACING] -> ALL_MSI/debug/MemTest.cc [ CXX] ALL_MSI/cpu/testers/rubytest/RubyTester.py.cc -> .o [ CXX] ALL_MSI/debug/MemTest.cc -> .o [SO Param] m5.objects.RubyTester, RubyTester -> ALL_MSI/python/_m5/param_RubyTester.cc [ TRACING] -> ALL_MSI/debug/RubyTest.hh [SO Param] m5.objects.RubyTester, RubyTester -> ALL_MSI/params/RubyTester.hh [ TRACING] -> ALL_MSI/debug/RubyTest.cc [CONFIG H] HAVE_PROTOBUF, 1 -> ALL_MSI/config/have_protobuf.hh [ TRACING] -> ALL_MSI/debug/TrafficGen.hh [ CXX] ALL_MSI/debug/RubyTest.cc -> .o [ENUMDECL] m5.objects.MemInterface, AddrMap -> ALL_MSI/enums/AddrMap.hh [SO Param] m5.objects.BaseTrafficGen, BaseTrafficGen -> ALL_MSI/params/BaseTrafficGen.hh [ CXX] ALL_MSI/cpu/testers/rubytest/Check.cc -> .o [ CXX] ALL_MSI/cpu/testers/rubytest/CheckTable.cc -> .o [ CXX] ALL_MSI/python/_m5/param_RubyTester.cc -> .o [ CXX] ALL_MSI/cpu/testers/rubytest/RubyTester.cc -> .o [ENUMDECL] m5.objects.BaseTrafficGen, StreamGenType -> ALL_MSI/enums/StreamGenType.hh [ CXX] ALL_MSI/cpu/testers/traffic_gen/base.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/base_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/dram_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/dram_rot_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/exit_gen.cc -> .o [ TRACING] -> ALL_MSI/debug/GUPSGen.hh [SO Param] m5.objects.GUPSGen, GUPSGen -> ALL_MSI/params/GUPSGen.hh [ CXX] ALL_MSI/cpu/testers/traffic_gen/hybrid_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/idle_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/gups_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/linear_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/nvm_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/random_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/stream_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/strided_gen.cc -> .o [ TRACING] -> ALL_MSI/debug/TrafficGen.cc [ CXX] ALL_MSI/debug/TrafficGen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/BaseTrafficGen.py.cc -> .o [SO Param] m5.objects.BaseTrafficGen, BaseTrafficGen -> ALL_MSI/python/_m5/param_BaseTrafficGen.cc [ENUM STR] m5.objects.BaseTrafficGen, StreamGenType -> ALL_MSI/enums/StreamGenType.cc [ TRACING] -> ALL_MSI/debug/GUPSGen.cc [ CXX] ALL_MSI/python/_m5/param_BaseTrafficGen.cc -> .o [ CXX] ALL_MSI/debug/GUPSGen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/GUPSGen.py.cc -> .o [SO Param] m5.objects.GUPSGen, GUPSGen -> ALL_MSI/python/_m5/param_GUPSGen.cc [SO Param] m5.objects.PyTrafficGen, PyTrafficGen -> ALL_MSI/params/PyTrafficGen.hh [ CXX] ALL_MSI/enums/StreamGenType.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/PyTrafficGen.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_GUPSGen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/pygen.cc -> .o [SO Param] m5.objects.PyTrafficGen, PyTrafficGen -> ALL_MSI/python/_m5/param_PyTrafficGen.cc [ CXX] ALL_MSI/cpu/testers/traffic_gen/TrafficGen.py.cc -> .o [SO Param] m5.objects.TrafficGen, TrafficGen -> ALL_MSI/python/_m5/param_TrafficGen.cc [ CXX] ALL_MSI/cpu/testers/traffic_gen/trace_gen.cc -> .o [SO Param] m5.objects.TrafficGen, TrafficGen -> ALL_MSI/params/TrafficGen.hh [ CXX] ALL_MSI/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_PyTrafficGen.cc -> .o [SO Param] m5.objects.GarnetSyntheticTraffic, GarnetSyntheticTraffic -> ALL_MSI/python/_m5/param_GarnetSyntheticTraffic.cc [ CXX] ALL_MSI/python/_m5/param_TrafficGen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/traffic_gen.cc -> .o [ TRACING] -> ALL_MSI/debug/GarnetSyntheticTraffic.hh [SO Param] m5.objects.GarnetSyntheticTraffic, GarnetSyntheticTraffic -> ALL_MSI/params/GarnetSyntheticTraffic.hh [ TRACING] -> ALL_MSI/debug/GarnetSyntheticTraffic.cc [ CXX] ALL_MSI/debug/GarnetSyntheticTraffic.cc -> .o [ CXX] ALL_MSI/cpu/probes/PcCountTracker.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_GarnetSyntheticTraffic.cc -> .o [ CXX] ALL_MSI/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc -> .o [SO Param] m5.objects.PcCountTracker, PcCountTracker -> ALL_MSI/python/_m5/param_PcCountTracker.cc [SO Param] m5.objects.PcCountTracker, PcCountTrackerManager -> ALL_MSI/python/_m5/param_PcCountTrackerManager.cc [SO Param] m5.objects.PcCountTracker, PcCountTracker -> ALL_MSI/params/PcCountTracker.hh [SO Param] m5.objects.PcCountTracker, PcCountTrackerManager -> ALL_MSI/params/PcCountTrackerManager.hh [ TRACING] -> ALL_MSI/debug/PcCountTracker.hh [ TRACING] -> ALL_MSI/debug/PcCountTracker.cc [ CXX] ALL_MSI/python/_m5/param_PcCountTrackerManager.cc -> .o [ CXX] ALL_MSI/debug/PcCountTracker.cc -> .o [ CXX] ALL_MSI/cpu/probes/pc_count_tracker.cc -> .o [ CXX] ALL_MSI/python/_m5/param_PcCountTracker.cc -> .o [ CXX] ALL_MSI/cpu/probes/pc_count_tracker_manager.cc -> .o [ CXX] ALL_MSI/learning_gem5/part2/SimpleObject.py.cc -> .o [SO Param] m5.objects.SimpleObject, SimpleObject -> ALL_MSI/python/_m5/param_SimpleObject.cc [SO Param] m5.objects.SimpleObject, SimpleObject -> ALL_MSI/params/SimpleObject.hh [ CXX] ALL_MSI/python/_m5/param_SimpleObject.cc -> .o [ CXX] ALL_MSI/learning_gem5/part2/HelloObject.py.cc -> .o [SO Param] m5.objects.HelloObject, HelloObject -> ALL_MSI/python/_m5/param_HelloObject.cc [SO Param] m5.objects.HelloObject, GoodbyeObject -> ALL_MSI/python/_m5/param_GoodbyeObject.cc [ CXX] ALL_MSI/learning_gem5/part2/SimpleMemobj.py.cc -> .o [SO Param] m5.objects.HelloObject, HelloObject -> ALL_MSI/params/HelloObject.hh [SO Param] m5.objects.HelloObject, GoodbyeObject -> ALL_MSI/params/GoodbyeObject.hh [SO Param] m5.objects.SimpleMemobj, SimpleMemobj -> ALL_MSI/python/_m5/param_SimpleMemobj.cc [ CXX] ALL_MSI/learning_gem5/part2/SimpleCache.py.cc -> .o [SO Param] m5.objects.SimpleCache, SimpleCache -> ALL_MSI/python/_m5/param_SimpleCache.cc [ CXX] ALL_MSI/python/_m5/param_HelloObject.cc -> .o [SO Param] m5.objects.SimpleMemobj, SimpleMemobj -> ALL_MSI/params/SimpleMemobj.hh [ CXX] ALL_MSI/python/_m5/param_GoodbyeObject.cc -> .o [ CXX] ALL_MSI/learning_gem5/part2/simple_object.cc -> .o [SO Param] m5.objects.SimpleCache, SimpleCache -> ALL_MSI/params/SimpleCache.hh [ TRACING] -> ALL_MSI/debug/HelloExample.hh [ CXX] ALL_MSI/python/_m5/param_SimpleMemobj.cc -> .o [ CXX] ALL_MSI/learning_gem5/part2/hello_object.cc -> .o [ CXX] ALL_MSI/learning_gem5/part2/goodbye_object.cc -> .o [ CXX] ALL_MSI/python/_m5/param_SimpleCache.cc -> .o [ TRACING] -> ALL_MSI/debug/SimpleMemobj.hh [ CXX] ALL_MSI/learning_gem5/part2/simple_memobj.cc -> .o [ TRACING] -> ALL_MSI/debug/SimpleCache.hh [ CXX] ALL_MSI/learning_gem5/part2/simple_cache.cc -> .o [ TRACING] -> ALL_MSI/debug/HelloExample.cc [ CXX] ALL_MSI/debug/HelloExample.cc -> .o [ TRACING] -> ALL_MSI/debug/SimpleMemobj.cc [ CXX] ALL_MSI/debug/SimpleMemobj.cc -> .o [ TRACING] -> ALL_MSI/debug/SimpleCache.cc [ CXX] ALL_MSI/debug/SimpleCache.cc -> .o [ CXX] ALL_MSI/mem/CommMonitor.py.cc -> .o [SO Param] m5.objects.CommMonitor, CommMonitor -> ALL_MSI/python/_m5/param_CommMonitor.cc [ TRACING] -> ALL_MSI/debug/CommMonitor.hh [SO Param] m5.objects.CommMonitor, CommMonitor -> ALL_MSI/params/CommMonitor.hh [ CXX] ALL_MSI/mem/AbstractMemory.py.cc -> .o [SO Param] m5.objects.AbstractMemory, AbstractMemory -> ALL_MSI/python/_m5/param_AbstractMemory.cc [ CXX] ALL_MSI/mem/comm_monitor.cc -> .o [ CXX] ALL_MSI/python/_m5/param_CommMonitor.cc -> .o [ CXX] ALL_MSI/python/_m5/param_AbstractMemory.cc -> .o [ CXX] ALL_MSI/mem/AddrMapper.py.cc -> .o [SO Param] m5.objects.AddrMapper, AddrMapper -> ALL_MSI/python/_m5/param_AddrMapper.cc [SO Param] m5.objects.AddrMapper, RangeAddrMapper -> ALL_MSI/python/_m5/param_RangeAddrMapper.cc [ CXX] ALL_MSI/mem/Bridge.py.cc -> .o [SO Param] m5.objects.AddrMapper, AddrMapper -> ALL_MSI/params/AddrMapper.hh [SO Param] m5.objects.AddrMapper, RangeAddrMapper -> ALL_MSI/params/RangeAddrMapper.hh [SO Param] m5.objects.Bridge, Bridge -> ALL_MSI/python/_m5/param_Bridge.cc [ CXX] ALL_MSI/python/_m5/param_AddrMapper.cc -> .o [ CXX] ALL_MSI/python/_m5/param_RangeAddrMapper.cc -> .o [SO Param] m5.objects.Bridge, Bridge -> ALL_MSI/params/Bridge.hh [ CXX] ALL_MSI/python/_m5/param_Bridge.cc -> .o [ CXX] ALL_MSI/mem/SysBridge.py.cc -> .o [SO Param] m5.objects.SysBridge, SysBridge -> ALL_MSI/python/_m5/param_SysBridge.cc [ TRACING] -> ALL_MSI/debug/SysBridge.cc [ TRACING] -> ALL_MSI/debug/SysBridge.hh [ CXX] ALL_MSI/debug/SysBridge.cc -> .o [SO Param] m5.objects.SysBridge, SysBridge -> ALL_MSI/params/SysBridge.hh [ CXX] ALL_MSI/mem/MemCtrl.py.cc -> .o [SO Param] m5.objects.MemCtrl, MemCtrl -> ALL_MSI/python/_m5/param_MemCtrl.cc [ENUM STR] m5.objects.MemCtrl, MemSched -> ALL_MSI/enums/MemSched.cc [ CXX] ALL_MSI/mem/HeteroMemCtrl.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_SysBridge.cc -> .o [ENUMDECL] m5.objects.MemCtrl, MemSched -> ALL_MSI/enums/MemSched.hh [SO Param] m5.objects.MemCtrl, MemCtrl -> ALL_MSI/params/MemCtrl.hh [ENUMDECL] m5.objects.DRAMInterface, PageManage -> ALL_MSI/enums/PageManage.hh [SO Param] m5.objects.MemInterface, MemInterface -> ALL_MSI/params/MemInterface.hh [ CXX] ALL_MSI/enums/MemSched.cc -> .o [ TRACING] -> ALL_MSI/debug/QOS.hh [SO Param] m5.objects.QoSMemCtrl, QoSMemCtrl -> ALL_MSI/params/QoSMemCtrl.hh [SO Param] m5.objects.HeteroMemCtrl, HeteroMemCtrl -> ALL_MSI/python/_m5/param_HeteroMemCtrl.cc [ CXX] ALL_MSI/mem/HBMCtrl.py.cc -> .o [ENUMDECL] m5.objects.QoSMemCtrl, QoSQPolicy -> ALL_MSI/enums/QoSQPolicy.hh [SO Param] m5.objects.HeteroMemCtrl, HeteroMemCtrl -> ALL_MSI/params/HeteroMemCtrl.hh [SO Param] m5.objects.NVMInterface, NVMInterface -> ALL_MSI/params/NVMInterface.hh [SO Param] m5.objects.QoSPolicy, QoSPolicy -> ALL_MSI/params/QoSPolicy.hh [SO Param] m5.objects.QoSTurnaround, QoSTurnaroundPolicy -> ALL_MSI/params/QoSTurnaroundPolicy.hh [SO Param] m5.objects.HBMCtrl, HBMCtrl -> ALL_MSI/python/_m5/param_HBMCtrl.cc [ CXX] ALL_MSI/mem/MemInterface.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MemCtrl.cc -> .o [SO Param] m5.objects.HBMCtrl, HBMCtrl -> ALL_MSI/params/HBMCtrl.hh Build step 'Execute shell' marked build as failure Archiving artifacts _______________________________________________ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
