[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Handle DRAM write queue drain and disabled power down

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69917?usp=email )

Change subject: mem: Handle DRAM write queue drain and disabled power down
......................................................................

mem: Handle DRAM write queue drain and disabled power down

Write queue drain logic seems off currently. An event is scheduled if
the write queue is empty instead of non-empty. There is no check to see
if draining is complete when bus is in write mode. Finally the power
down check on drain always fails if DRAM powerdown is disabled.

This changeset reverses the drain conditional for the write queue to
schedule an event if the write queue is *not* empty and checks in the
event processing method that the queues are all empty so that
signalDrainDone can be called. Lastly the powerdown state is ignored if
DRAM powerdown is disabled. Powerdown is disabled in the GPU_VIPER
protocol by default. This changeset successfully drains and checkpoints
a GPUFS simulation using GPU_VIPER protocol.

Change-Id: I5459856a694c9054b28677049a06b99b9ad91bbb
---
M src/mem/dram_interface.hh
M src/mem/mem_ctrl.cc
2 files changed, 14 insertions(+), 2 deletions(-)



diff --git a/src/mem/dram_interface.hh b/src/mem/dram_interface.hh
index fa9d319..206f8e8 100644
--- a/src/mem/dram_interface.hh
+++ b/src/mem/dram_interface.hh
@@ -380,7 +380,11 @@
          * @param Return true if the rank is idle from a bank
          *        and power point of view
          */
-        bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
+        bool
+        inPwrIdleState() const
+        {
+            return !dram.enableDRAMPowerdown || pwrState == PWR_IDLE;
+        }

         /**
          * Trigger a self-refresh exit if there are entries enqueued
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 543d637..074a31f 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -908,6 +908,13 @@
         }
     }

+    if (drainState() == DrainState::Draining && !totalWriteQueueSize &&
+        !totalReadQueueSize && respQEmpty()) {
+
+        DPRINTF(Drain, "MemCtrl controller done draining\n");
+        signalDrainDone();
+    }
+
     // updates current state
     busState = busStateNext;

@@ -1420,7 +1427,8 @@

         // the only queue that is not drained automatically over time
         // is the write queue, thus kick things into action if needed
-        if (!totalWriteQueueSize && !nextReqEvent.scheduled()) {
+        if (totalWriteQueueSize && !nextReqEvent.scheduled()) {
+            DPRINTF(Drain,"Scheduling nextReqEvent from drain\n");
             schedule(nextReqEvent, curTick());
         }


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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5459856a694c9054b28677049a06b99b9ad91bbb
Gerrit-Change-Number: 69917
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
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