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Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email
to review the following change.
Change subject: arch-arm: Remove clear32/64 methods
......................................................................
arch-arm: Remove clear32/64 methods
Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
3 files changed, 74 insertions(+), 111 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d87e9c5..ffd9cfc 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -131,8 +131,6 @@
void
ISA::clear()
{
- const Params &p(params());
-
// Invalidate cached copies of miscregs in the TLBs
if (tc) {
getMMUPtr(tc)->invalidateMiscReg();
@@ -142,111 +140,7 @@
miscRegs[idx] = lookUpMiscReg[idx].reset();
}
- if (FullSystem && system->highestELIs64()) {
- // Initialize AArch64 state
- clear64(p);
- return;
- }
-
- // Initialize AArch32 state...
- clear32(p);
-}
-
-void
-ISA::clear32(const ArmISAParams &p)
-{
- CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
-
- if (FullSystem) {
- miscRegs[MISCREG_MVBAR] = system->resetAddr();
- }
-
- miscRegs[MISCREG_CPSR] = cpsr;
- updateRegMap(cpsr);
-
- SCTLR sctlr = 0;
- sctlr.u = 1;
- sctlr.xp = 1;
- sctlr.rao2 = 1;
- sctlr.rao3 = 1;
- sctlr.rao4 = 0xf; // SCTLR[6:3]
- sctlr.uci = 1;
- sctlr.dze = 1;
- miscRegs[MISCREG_SCTLR_NS] = sctlr;
- miscRegs[MISCREG_HCPTR] = 0;
-
- miscRegs[MISCREG_CPACR] = 0;
-
- miscRegs[MISCREG_FPSID] = p.fpsid;
-
- if (release->has(ArmExtension::LPAE)) {
- TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
- ttbcr.eae = 0;
- miscRegs[MISCREG_TTBCR_NS] = ttbcr;
- // Enforce consistency with system-level settings
- miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) |
0x5;
- }
-
- if (release->has(ArmExtension::SECURITY)) {
- miscRegs[MISCREG_SCTLR_S] = sctlr;
- miscRegs[MISCREG_SCR] = 0;
- miscRegs[MISCREG_VBAR_S] = 0;
- } else {
- // we're always non-secure
- miscRegs[MISCREG_SCR] = 1;
- }
-
- //XXX We need to initialize the rest of the state.
-}
-
-void
-ISA::clear64(const ArmISAParams &p)
-{
- CPSR cpsr = 0;
- Addr rvbar = system->resetAddr();
- switch (system->highestEL()) {
- // Set initial EL to highest implemented EL using associated stack
- // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
- // value
- case EL3:
- cpsr.mode = MODE_EL3H;
- miscRegs[MISCREG_RVBAR_EL3] = rvbar;
- break;
- case EL2:
- cpsr.mode = MODE_EL2H;
- miscRegs[MISCREG_RVBAR_EL2] = rvbar;
- break;
- case EL1:
- cpsr.mode = MODE_EL1H;
- miscRegs[MISCREG_RVBAR_EL1] = rvbar;
- break;
- default:
- panic("Invalid highest implemented exception level");
- break;
- }
-
- // Initialize rest of CPSR
- cpsr.daif = 0xf; // Mask all interrupts
- cpsr.ss = 0;
- cpsr.il = 0;
- miscRegs[MISCREG_CPSR] = cpsr;
- updateRegMap(cpsr);
-
- // Initialize other control registers
- miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
- if (release->has(ArmExtension::SECURITY)) {
- miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
- miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
- } else if (release->has(ArmExtension::VIRTUALIZATION)) {
- // also MISCREG_SCTLR_EL2 (by mapping)
- miscRegs[MISCREG_HSCTLR] = 0x30c50830;
- } else {
- // also MISCREG_SCTLR_EL1 (by mapping)
- miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 |
init
- // Always non-secure
- miscRegs[MISCREG_SCR_EL3] = 1;
- }
+ updateRegMap(miscRegs[MISCREG_CPSR]);
}
void
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 55fbd03..8ed37ba 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -170,9 +170,6 @@
void clear() override;
protected:
- void clear32(const ArmISAParams &p);
- void clear64(const ArmISAParams &p);
-
void addressTranslation(MMU::ArmTranslationType tran_type,
BaseMMU::Mode mode, Request::Flags flags, RegVal val);
void addressTranslation64(MMU::ArmTranslationType tran_type,
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 2995177..8edbadc 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2079,6 +2079,34 @@
return *this;
}
+static CPSR
+resetCPSR(ArmSystem *system)
+{
+ CPSR cpsr = 0;
+ switch (system->highestEL()) {
+ // Set initial EL to highest implemented EL using associated stack
+ // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
+ // value
+ case EL3:
+ cpsr.mode = MODE_EL3H;
+ break;
+ case EL2:
+ cpsr.mode = MODE_EL2H;
+ break;
+ case EL1:
+ cpsr.mode = MODE_EL1H;
+ break;
+ default:
+ panic("Invalid highest implemented exception level");
+ break;
+ }
+
+ // Initialize rest of CPSR
+ cpsr.daif = 0xf; // Mask all interrupts
+ cpsr.ss = 0;
+ cpsr.il = 0;
+ return cpsr;
+}
void
ISA::initializeMiscRegMetadata()
@@ -2143,6 +2171,7 @@
*/
InitReg(MISCREG_CPSR)
+ .reset(resetCPSR(system))
.allPrivileges();
InitReg(MISCREG_SPSR)
.allPrivileges();
@@ -2163,6 +2192,7 @@
InitReg(MISCREG_ELR_HYP)
.allPrivileges();
InitReg(MISCREG_FPSID)
+ .reset(p.fpsid)
.allPrivileges();
InitReg(MISCREG_FPSCR)
.allPrivileges();
@@ -2487,6 +2517,7 @@
.reset(1) // Separate Instruction and Data TLBs
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_MPIDR)
+ .reset(0x80000000)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_REVIDR)
.unimplemented()
@@ -2502,7 +2533,12 @@
InitReg(MISCREG_ID_AFR0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR0)
- .reset(p.id_mmfr0)
+ .reset([p,release=release](){
+ RegVal mmfr0 = p.id_mmfr0;
+ if (release->has(ArmExtension::LPAE))
+ mmfr0 = (mmfr0 & ~0xf) | 0x5;
+ return mmfr0;
+ }())
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_MMFR1)
.reset(p.id_mmfr1)
@@ -2585,11 +2621,37 @@
.res1(0x00400800 | (SPAN ? 0 : 0x800000)
| (LSMAOE ? 0 : 0x10)
| (nTLSMD ? 0 : 0x8));
+
+ auto sctlr_reset = [aarch64=highestELIs64] ()
+ {
+ SCTLR sctlr = 0;
+ if (aarch64) {
+ sctlr.afe = 1;
+ sctlr.tre = 1;
+ sctlr.span = 1;
+ sctlr.uwxn = 1;
+ sctlr.ntwe = 1;
+ sctlr.ntwi = 1;
+ sctlr.cp15ben = 1;
+ sctlr.sa0 = 1;
+ } else {
+ sctlr.u = 1;
+ sctlr.xp = 1;
+ sctlr.uci = 1;
+ sctlr.dze = 1;
+ sctlr.rao2 = 1;
+ sctlr.rao3 = 1;
+ sctlr.rao4 = 0xf;
+ }
+ return sctlr;
+ }();
InitReg(MISCREG_SCTLR_NS)
+ .reset(sctlr_reset)
.bankedChild()
.privSecure(!aarch32EL3)
.nonSecure().exceptUserMode();
InitReg(MISCREG_SCTLR_S)
+ .reset(sctlr_reset)
.bankedChild()
.secure().exceptUserMode();
InitReg(MISCREG_ACTLR)
@@ -2606,6 +2668,7 @@
InitReg(MISCREG_SDCR)
.mon();
InitReg(MISCREG_SCR)
+ .reset(release->has(ArmExtension::SECURITY) ? 0 : 1)
.mon().secure().exceptUserMode()
.res0(0xff40) // [31:16], [6]
.res1(0x0030); // [5:4]
@@ -2614,6 +2677,7 @@
InitReg(MISCREG_NSACR)
.allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
InitReg(MISCREG_HSCTLR)
+ .reset(0x30c50830)
.hyp().monNonSecure()
.res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
| (IESB ? 0 : 0x200000)
@@ -3043,6 +3107,7 @@
.bankedChild()
.secure().exceptUserMode();
InitReg(MISCREG_MVBAR)
+ .reset(FullSystem ? system->resetAddr() : 0)
.mon().secure()
.hypRead(FullSystem && system->highestEL() == EL2)
.privRead(FullSystem && system->highestEL() == EL1)
@@ -3925,6 +3990,7 @@
.hyp().mon()
.mapsTo(MISCREG_HACR);
InitReg(MISCREG_SCTLR_EL3)
+ .reset(0x30c50830)
.mon()
.res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
| (IESB ? 0 : 0x200000)
@@ -4369,6 +4435,8 @@
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_VBAR_NS);
InitReg(MISCREG_RVBAR_EL1)
+ .reset(FullSystem && system->highestEL() == EL1 ?
+ system->resetAddr() : 0)
.privRead(FullSystem && system->highestEL() == EL1);
InitReg(MISCREG_ISR_EL1)
.allPrivileges().exceptUserMode().writes(0);
@@ -4377,10 +4445,14 @@
.res0(0x7ff)
.mapsTo(MISCREG_HVBAR);
InitReg(MISCREG_RVBAR_EL2)
+ .reset(FullSystem && system->highestEL() == EL2 ?
+ system->resetAddr() : 0)
.hypRead(FullSystem && system->highestEL() == EL2);
InitReg(MISCREG_VBAR_EL3)
.mon();
InitReg(MISCREG_RVBAR_EL3)
+ .reset(FullSystem && system->highestEL() == EL3 ?
+ system->resetAddr() : 0)
.mon().writes(0);
InitReg(MISCREG_RMR_EL3)
.mon();
--
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https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a
Gerrit-Change-Number: 70470
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Attention: Richard Cooper <richard.coo...@arm.com>
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