Attention is currently required from: Richard Cooper.
Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email
to review the following change.
Change subject: arch-arm: Rename AdvSIMD instruction pool
......................................................................
arch-arm: Rename AdvSIMD instruction pool
The decoding function was wrongly named decodeNeon3SameExtra,
referring to the "AdvSIMD three same Extra" instruction pool
This might be an old name as I can only find the
"AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension
Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/neon64.isa
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 9ad2de2..47d509e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2461,7 +2461,7 @@
return new Unknown64(machInst);
}
} else if (bits(machInst, 15) == 1) {
- return decodeNeon3SameExtra<DecoderFeatures>(machInst);
+ return decodeNeon3RegExtension<DecoderFeatures>(machInst);
} else if (bits(machInst, 10) == 1) {
if (bits(machInst, 23, 22))
return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/neon64.isa
b/src/arch/arm/isa/formats/neon64.isa
index 72b7e28..c200da7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -39,9 +39,9 @@
// AdvSIMD three same
template <typename DecoderFeatures>
StaticInstPtr decodeNeon3Same(ExtMachInst machInst);
- // AdvSIMD three same Extra
+ // AdvSIMD three register extension
template <typename DecoderFeatures>
- StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst);
+ StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst);
// AdvSIMD three different
inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst);
// AdvSIMD two-reg misc
@@ -507,7 +507,7 @@
template <typename DecoderFeatures>
StaticInstPtr
- decodeNeon3SameExtra(ExtMachInst machInst)
+ decodeNeon3RegExtension(ExtMachInst machInst)
{
uint8_t q = bits(machInst, 30);
uint8_t size = bits(machInst, 23, 22);
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Gerrit-Change-Number: 70724
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Attention: Richard Cooper <richard.coo...@arm.com>
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