Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email )
Change subject: arch-arm: Apply FEAT_IDST to AArch32 state registers
......................................................................
arch-arm: Apply FEAT_IDST to AArch32 state registers
When FEAT_IDST got implemented [1], we forgot to add the
logic for ID registers tracking AArch32 state/capabilities
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/70723
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I19bddf67ecc379a14f91cfede385692536982101
---
M src/arch/arm/regs/misc.cc
1 file changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index f32aa72..f1c69cc 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3911,83 +3911,104 @@
.mapsTo(MISCREG_MIDR);
InitReg(MISCREG_MPIDR_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.mapsTo(MISCREG_MPIDR);
InitReg(MISCREG_REVIDR_EL1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid1))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_PFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_PFR0);
InitReg(MISCREG_ID_PFR1_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_PFR1);
InitReg(MISCREG_ID_DFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_DFR0);
InitReg(MISCREG_ID_AFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_AFR0);
InitReg(MISCREG_ID_MMFR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR0);
InitReg(MISCREG_ID_MMFR1_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR1);
InitReg(MISCREG_ID_MMFR2_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR2);
InitReg(MISCREG_ID_MMFR3_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR3);
InitReg(MISCREG_ID_MMFR4_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_MMFR4);
InitReg(MISCREG_ID_ISAR0_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR0);
InitReg(MISCREG_ID_ISAR1_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR1);
InitReg(MISCREG_ID_ISAR2_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR2);
InitReg(MISCREG_ID_ISAR3_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR3);
InitReg(MISCREG_ID_ISAR4_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR4);
InitReg(MISCREG_ID_ISAR5_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR5);
InitReg(MISCREG_ID_ISAR6_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.mapsTo(MISCREG_ID_ISAR6);
InitReg(MISCREG_MVFR0_EL1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_MVFR0);
InitReg(MISCREG_MVFR1_EL1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_MVFR1);
InitReg(MISCREG_MVFR2_EL1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64PFR0_EL1)
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I19bddf67ecc379a14f91cfede385692536982101
Gerrit-Change-Number: 71178
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
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