[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Make virtual method RISC-V private

[Gerrit]

Adrià Armejach has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71818?usp=email )

Change subject: arch-riscv: Make virtual method RISC-V private
......................................................................

arch-riscv: Make virtual method RISC-V private

* Prior commit defined a shared virtual method that is only used in
  RISC-V. This patch makes the method only visible to the RISC-V ISA.

Change-Id: Ie31e1e1e5933d7c3b9f5af0c20822d3a6a382eee
---
M src/arch/generic/isa.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.hh
3 files changed, 9 insertions(+), 9 deletions(-)



diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 58f66fc..e9e4d95 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -70,7 +70,6 @@
   public:
     virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
     virtual void clear() {}
-    virtual void clearLoadReservation(ContextID cid) {}

     virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
     virtual RegVal readMiscReg(RegIndex idx) = 0;
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 8fb8f81..a929902 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -154,7 +154,8 @@
         }

         // Clear load reservation address
-        tc->getIsaPtr()->clearLoadReservation(tc->contextId());
+        auto isa = static_cast<RiscvISA::ISA*>(tc->getIsaPtr());
+        isa->clearLoadReservation(tc->contextId());

         // Set PC to fault handler address
         Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 7ef5c52..31001c0 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -92,13 +92,6 @@
         return new PCState(new_inst_addr, rv_type);
     }

-    void
-    clearLoadReservation(ContextID cid) override
-    {
-        Addr& load_reservation_addr = load_reservation_addrs[cid];
-        load_reservation_addr = INVALID_RESERVATION_ADDR;
-    }
-
   public:
     RegVal readMiscRegNoEffect(RegIndex idx) const override;
     RegVal readMiscReg(RegIndex idx) override;
@@ -142,6 +135,13 @@
     void resetThread() override;

     RiscvType rvType() const { return rv_type; }
+
+    void
+    clearLoadReservation(ContextID cid)
+    {
+        Addr& load_reservation_addr = load_reservation_addrs[cid];
+        load_reservation_addr = INVALID_RESERVATION_ADDR;
+    }
 };

 } // namespace RiscvISA

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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie31e1e1e5933d7c3b9f5af0c20822d3a6a382eee
Gerrit-Change-Number: 71818
Gerrit-PatchSet: 1
Gerrit-Owner: Adrià Armejach <adria.armej...@bsc.es>
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