Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71998?usp=email )
Change subject: cpu-o3: add decode stall in fetch stage
......................................................................
cpu-o3: add decode stall in fetch stage
Change-Id: Ibbd532092449bcee5210cde85beeb5e8429fca8c
---
M src/cpu/o3/fetch.cc
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 8cd84cb..41841f2 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -1176,11 +1176,13 @@
auto *dec_ptr = decoder[tid];
const Addr pc_mask = dec_ptr->pcMask();
+ auto fetchStall = false;
+
// Loop through instruction memory from the cache.
// Keep issuing while fetchWidth is available and branch is not
// predicted taken
while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
- && !predictedBranch && !quiesce) {
+ && !predictedBranch && !quiesce && !fetchStall) {
// We need to process more memory if we aren't going to get a
// StaticInst from the rom, the current macroop, or what's already
// in the decoder.
@@ -1228,6 +1230,7 @@
pcOffset = 0;
}
} else {
+ fetchStall = dec_ptr->isStalled();
// We need more bytes for this instruction so
blkOffset and
// pcOffset will be updated
break;
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibbd532092449bcee5210cde85beeb5e8429fca8c
Gerrit-Change-Number: 71998
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
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