Hi Peter,
I am not sure, but could the issue be this one:
https://www.mail-archive.com/gem5-dev@gem5.org/msg16924.html
At least as far as I know, the problem that the X86-O3-CPU cannot handle
jumps to the same location still exists.
Best regards,
Nils
On 3/25/24 14:29, Peter Wang via gem5-dev wrote:
|I'm using the configuration based on X86-ubuntu-run-with-kvm.py from
the gem5_library. Here is my configuration. from gem5.coherence_protocol
import CoherenceProtocol from gem5.components.boards.x86_board import
X86Board from gem5.components.memory.single_channel import
SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import
CPUTypes from gem5.components.processors.simple_processor import (
SimpleProcessor, ) from gem5.isas import ISA from
gem5.resources.resource import ( DiskImageResource, KernelResource, )
from gem5.simulate.simulator import Simulator from gem5.utils.requires
import requires from gem5.components.boards.kernel_disk_workload import
KernelDiskWorkload # This runs a check to ensure the gem5 binary is
compiled to X86 and to the # MESI Two Level coherence protocol.
requires( isa_required=ISA.X86,
coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL, ) from
gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy
import ( MESITwoLevelCacheHierarchy, ) cache_hierarchy =
MESITwoLevelCacheHierarchy( l1d_size="16kB", l1d_assoc=8,
l1i_size="16kB", l1i_assoc=8, l2_size="256kB", l2_assoc=16,
num_l2_banks=1, ) # Setup the system memory. memory =
SingleChannelDDR3_1600(size="3GB") processor = SimpleProcessor(
cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1, ) board = X86Board(
clk_freq="3GHz", processor=processor, memory=memory,
cache_hierarchy=cache_hierarchy, )
board.set_kernel_disk_workload(kernel=KernelResource(local_path="/workspace/example"), disk_image=DiskImageResource(local_path="/workspace/rootfs.ext2"), ) simulator = Simulator( board=board, on_exit_event={ # Here we want override the default behavior for the first m5 exit # exit event. Instead of exiting the simulator, we just want to # switch the processor. The 2nd m5 exit after will revert to using # default behavior where the simulator run will exit. # ExitEvent.EXIT: (func() for func in [processor.switch]) }, ) simulator.run()|
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