[gem5-users] How to set vector length for riscv v extention in Gem5

[Xiaokang Fan via gem5-users]

Hi all,

I have a question regarding the configuration of vector lengths for the
RISC-V V extension in Gem5.


I know that for ARM SVE, Gem5 provides options such as 'system.sve_vl' and
'system.cpu[:].isa[:].sve_vl_se' to set the vector length. However, I am
curious if there are any analogous settings available for customizing the
vector length of the RISC-V V extension.


I would greatly appreciate any help.


Best regards,


Xiaokang

_______________________________________________
gem5-users mailing list -- gem5-us...@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org