system.cpu1: completed 1441000 read accesses @52151501002 system.cpu7: completed 1440000 read accesses @52155444000 system.cpu2: completed 1439000 read accesses @52156863003 system.cpu6: completed 1437000 read accesses @52157426000 system.cpu4: completed 1443000 read accesses @52160669006 system.cpu0: completed 1440000 read accesses @52168664002 system.cpu3: completed 1443000 read accesses @52171947004 system.cpu5: completed 1441000 read accesses @52186313001 system.cpu1: completed 1442000 read accesses @52190818002 system.cpu7: completed 1441000 read accesses @52191294004 system.cpu6: completed 1438000 read accesses @52192658003 system.cpu2: completed 1440000 read accesses @52195055002 system.cpu4: completed 1444000 read accesses @52195763000panic: system.cpu7: read of 405507 (blk 405500) @ cycle 52199082001 returns f5, expected 55
@ cycle 52199082001 [completeRequest:build/ALPHA_SE/cpu/memtest/memtest.cc, line 214] Program aborted at cycle 52199082001 Aborted (core dumped)
memtest.diff
Description: Binary data
Ali On Mar 12, 2008, at 2:02 AM, Ali Saidi wrote:
Can you give us some information about what you're running configuration wise? Your config files would actually be good. You're stressing something that hasn't really been stressed before, so the first step is for us to be able to reliably duplicate the issue.Ali On Mar 12, 2008, at 1:27 AM, Sujay Phadke wrote:I commented the assertion statement out. The benchmarks do complete, but calculations are incorrect for some of them. For example, radix outputs the following:warn: ignoring syscall sigaction(5, 4831387552, ...) warn: ignoring syscall sigaction(13, 4831387552, ...) error with key 6475, value 102548 96863 error with key 7229, value 99786 97034 error with key 28571, value 178321 165003 error with key 28572, value 165003 141160 error with key 28573, value 141160 140297 error with key 51316, value 162386 146546 error with key 55007, value 165327 139551 error with key 55009, value 183538 165330 This didnt happen with beta 4. - Sujay----- Original Message ----- From: "Steve Reinhardt" <[EMAIL PROTECTED] >To: "M5 users mailing list" <[EMAIL PROTECTED]> Sent: Tuesday, March 11, 2008 5:38 PM Subject: Re: [m5-users] error running splash2 in beta 5That could be related to the cache changes I made to get writebacks to allocate in the cache. Looking at the assert, I'd say there's a 50/50chance that the bug is simply that the assertion isn't valid anymore rather than anything actually being broken. Unfortunately I won't have time to look at it in detail for a few days. Can you try just commenting out the assertion and seeing if those benchmarks complete successfully? Thanks, SteveOn Tue, Mar 11, 2008 at 2:08 PM, Sujay Phadke <[EMAIL PROTECTED] > wrote:Hi all, I am trying to run the splash2 in m5 beta 5. On 5 of the benchmarks, I get the following error: m5.opt: build/ALPHA_SE/mem/cache/cache_impl.hh:1282: Packet* Cache<TagStore>::getTimingPacket() [with TagStore = LRU]: Assertion `tags->findBlock(mshr->addr) == __null' failed. and M5 aborts. Can someone explain what this means? - Sujay _______________________________________________ m5-users mailing list [EMAIL PROTECTED] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users_______________________________________________ m5-users mailing list [EMAIL PROTECTED] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users_______________________________________________ m5-users mailing list [EMAIL PROTECTED] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users_______________________________________________ m5-users mailing list [EMAIL PROTECTED] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
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