Right now, I'm at a point in the kernel where it's trying calculate
the mapping between ticks of the time stamp counter (TSC) MSR and time
from a fake 8254 programmable interval timer provided by the chipset.
Neither of these things are implemented, so the calculations end up
being (some_constant) / ((0 - 0) / 50) which blows up. This is a problem
I'll have to address by implementing some of these things.
Beyond that, when this function does work, it's supposed to do the
following. It sets up the timer to wiggle it's output after a certain
amount of time on the output connected to the PC speaker, records the
TSC value, reads the state of the speaker driver (on or off) until the
timer fires, reads the new TSC value, and then finds the conversion
factor. This seems like it might take a long time just spinning waiting
for the timer to go off, so it would be nice to put in one of those
function skipping things that I know m5 supports for Alpha. Would
somebody describe how that works?
Also, there are little bits of stuff connected to each other all
over the place outside of the memory system. For instance, the timer,
which is at one set of addresses, needs to be able to toggle the
"speaker" which is readable from a completely separate address. I could
either glob this stuff into one big device, or I need to establish
connections between these devices that circumvents busses and all that.
I don't think that's a problem at all, but it seemed a little unorthodox
so I thought I'd bring it up.
Also, there is a weird way to access the CMOS which linux has used
to get at the RTC information. First, you set an address at one IO port,
and then the other IO port reads and writes that offset in the CMOS. I
think that sort of access mechanism is going to be very common for x86,
so I still think there needs to be some sort of gateway device that does
this address space hiding, or translation, or bridging, or whatever
you'd like to call it. This is just an IsaFake at the moment so that's fine.
Finally, I need to figure out how the ISA/legacy bus fits into the
address spaces. I think it's basically mapped into the IO address space,
but unfortunately I don't have access to the books Nate sent me from HP
at the moment which have all that sort of information. I have a bunch of
interviewing coming up which will keep me away from campus, but I'll try
to get in there and grab those books one of these days. One thing I'm
concerned about is how to handle needing an IsaFake as the default
responder for the ISA bus, but also making the PCI stuff fits in there.
I was under the impression that the PCI space was a default responder or
something on one of the busses. I'm imagining my question here doesn't
make perfect sense since I'm a little fuzzy on how this stuff is
supposed to work, but hopefully that also means it's not that hard and I
just need some thorough explanation.
Gabe
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