> Would somebody describe how that works?
Basically, there is an event queue in each CPU that triggers on the
PC. When an instruction comes in at one of the watched PCs is
executed, it calls a function instead of calling the normal execute
function. This function fiddles with the return value register and in
the case of a branch, causes the branch to not happen.
> Also, there are little bits of stuff connected to each other all
> over the place outside of the memory system. For instance, the timer,
> which is at one set of addresses, needs to be able to toggle the
> "speaker" which is readable from a completely separate address. I could
> either glob this stuff into one big device, or I need to establish
> connections between these devices that circumvents busses and all that.
> I don't think that's a problem at all, but it seemed a little unorthodox
> so I thought I'd bring it up.
I'd say that you should just build one big device called X86Legacy and
do everything in there. Given that things are all over the palace,
and the performance doesn't really matter, this seems to be the
easiest approach.
> I think that sort of access mechanism is going to be very common for x86,
> so I still think there needs to be some sort of gateway device that does
> this address space hiding, or translation, or bridging, or whatever
> you'd like to call it. This is just an IsaFake at the moment so that's fine.
There are two ways to do this. One is to put the stuff into the TLB,
the other is to create a device that responds to those addresses and
then creates new requests based on those addresses. This may be the
best option if there are a lot of these situations. I wonder what the
real machine does.
> One thing I'm
> concerned about is how to handle needing an IsaFake as the default
> responder for the ISA bus, but also making the PCI stuff fits in there.
I'm not clear on what you're saying here. Why do you want a device to
be a default responder? The default responder on the various busses
either returns all ones or all zeros in the case of an invalid address
so it can be probed.
> I was under the impression that the PCI space was a default responder or
> something on one of the busses.
On any bus that has PCI devices, there is a default responder, but
usually that bus is separated from other busses like the memory bus by
a bus bridge.
Nate
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