I may have known the answer to this once (or maybe I'm just dreaming),
but I am currently a bit mind-boggled to why O3 has a different number
of sim_insts (simulated instructions) then the SimpleCPUs for the same
workloads.
Have the regressions not been updated? Have stats got messed up along
the way???
The stdout and stderr outputs seem the same regardless of CPU so maybe
this is just a stat thing.
I detected this by grep'ing for "sim_inst" in the regressions (tests)
directory long and quick folders. Here are a couple of notable
discrepancies:
quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:20:sim_insts
5623 # Number
of instructions simulated
quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt:8:sim_insts
5641 #
Number of instructions simulated
quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:8:sim_insts
5641 #
Number of instructions simulated
long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:20:sim_insts
375574819 # Number of
instructions simulated
long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt:8:sim_insts
398664595 # Number
of instructions simulated
long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt:8:sim_insts
398664609 # Number
of instructions simulated
long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:20:sim_insts
1736043781 # Number
of instructions simulated
long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt:8:sim_insts
1819780127 #
Number of instructions simulated
long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt:8:sim_insts
1819780127 #
Number of instructions simulated
Lastly, I also noticed we dont have a low % of the SPEC regressions
for the O3 CPU (in comparison to the SimpleCPU)... We (or maybe just
me?!) should probably get to work on updating that since there has
been loads of detail getting that to be flexible with all kind of
architectures. It would be a shame to have to re-engineer and take the
time to fix things
that may have previously worked...
--
----------
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science & Engineering
University of Michigan
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev