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FS#209 - Implement Sparc memory syncronization instructions User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Implement Sparc memory syncronization instructions Task Type - Bug Category - CPU Status - Assigned Assigned To - Ali Saidi Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - a. flush -- Flushes the icache. In reality this isn't required as long as the icache snoops the dcache b. prefetch/prefetcha c. stbar/membar Flush provides an address, so it needs to just send a writeback and invalidate command to all the icaches. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/209 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
