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FS#217 - SPARC fault priorities User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - SPARC fault priorities Task Type - Bug Category - CPU Status - New Assigned To - Lisa Hsu Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - I don't know how much we need to worry about this, but instruction tlb misses are higher priority than interrupts I put some code like if (curTick == XXXXX) return NoFault; in interrupts to make M5 line up with legion in this regard. The problem is we get the interrupt faults and the tlb faults in different places (interrupt first currently). Once we get the interrupt fault we can't undo that. (The interrupt controller thinks its been handled now). So we need to split this up into a getInterrutp() and then handleInterrupt() which actually marks that interrupt as taken or something. I don't know how the detailed cpu handles interrupts as well. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/217 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
