changeset ebec0a848220 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ebec0a848220
summary: Checkpoinging/SWIG: Undo part of changeset 5464 since it broke 
checkpointing.

changeset d9de38fba64c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d9de38fba64c
summary: Automated merge with http://repo.m5sim.org/m5-stable

diffstat:

71 files changed, 1068 insertions(+), 804 deletions(-)
src/base/inet.hh                                                                
                        |   15 
src/cpu/base.cc                                                                 
                        |    8 
src/cpu/o3/fetch.hh                                                             
                        |    1 
src/cpu/o3/lsq.hh                                                               
                        |    1 
src/cpu/simple/AtomicSimpleCPU.py                                               
                        |    1 
src/cpu/simple/atomic.cc                                                        
                        |    2 
src/cpu/simple/atomic.hh                                                        
                        |    1 
src/cpu/simple_thread.cc                                                        
                        |    2 
src/dev/SConscript                                                              
                        |    2 
src/dev/SimConsole.py                                                           
                        |   19 -
src/dev/Terminal.py                                                             
                        |   19 +
src/dev/alpha/AlphaBackdoor.py                                                  
                        |   19 +
src/dev/alpha/AlphaConsole.py                                                   
                        |   19 -
src/dev/alpha/SConscript                                                        
                        |    2 
src/dev/alpha/Tsunami.py                                                        
                        |    3 
src/dev/alpha/backdoor.cc                                                       
                        |  155 ++++++++
src/dev/alpha/backdoor.hh                                                       
                        |   63 +++
src/dev/alpha/console.cc                                                        
                        |  155 --------
src/dev/alpha/console.hh                                                        
                        |   63 ---
src/dev/alpha/tsunami.cc                                                        
                        |    1 
src/dev/etherdevice.cc                                                          
                        |  183 ++++++++++
src/dev/etherpkt.hh                                                             
                        |    8 
src/dev/mips/Malta.py                                                           
                        |    3 
src/dev/mips/MipsBackdoor.py                                                    
                        |   19 +
src/dev/mips/MipsConsole.py                                                     
                        |   19 -
src/dev/mips/SConscript                                                         
                        |    2 
src/dev/mips/backdoor.cc                                                        
                        |  148 ++++++++
src/dev/mips/backdoor.hh                                                        
                        |   63 +++
src/dev/mips/console.cc                                                         
                        |  148 --------
src/dev/mips/console.hh                                                         
                        |   63 ---
src/dev/mips/malta.cc                                                           
                        |    1 
src/dev/pktfifo.cc                                                              
                        |   17 
src/dev/pktfifo.hh                                                              
                        |   26 +
src/dev/simconsole.cc                                                           
                        |  168 ---------
src/dev/simconsole.hh                                                           
                        |   73 ---
src/dev/sinic.cc                                                                
                        |    2 
src/dev/sparc/T1000.py                                                          
                        |    2 
src/dev/sparc/t1000.cc                                                          
                        |    1 
src/dev/terminal.cc                                                             
                        |  166 +++++++++
src/dev/terminal.hh                                                             
                        |   73 +++
src/dev/uart.cc                                                                 
                        |    4 
src/dev/uart8250.cc                                                             
                        |    2 
src/dev/x86/PC.py                                                               
                        |    5 
src/mem/bus.cc                                                                  
                        |    1 
src/mem/cache/cache_impl.hh                                                     
                        |    4 
src/mem/mem_object.cc                                                           
                        |    1 
src/mem/mem_object.hh                                                           
                        |    5 
src/mem/physical.cc                                                             
                        |    5 
src/mem/port.cc                                                                 
                        |    9 
src/mem/port.hh                                                                 
                        |    1 
src/python/m5/SimObject.py                                                      
                        |    7 
src/python/m5/params.py                                                         
                        |    2 
src/python/swig/core.i                                                          
                        |    1 
src/python/swig/event.i                                                         
                        |    1 
src/sim/compile_info.cc                                                         
                        |   28 +
src/sim/sim_object.hh                                                           
                        |    2 
src/sim/sim_object_params.hh                                                    
                        |   25 +
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
         |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
                    |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
              |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal 
                        |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
         |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
                    |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
              |    2 
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal 
                        |    2 
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
 |    2 
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
  |    2 
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
            |    2 
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
                       |    6 
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
                       |    3 
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
             |    2 

diffs (truncated from 8931 to 300 lines):

diff -r 47c5168d092c -r d9de38fba64c configs/common/FSConfig.py
--- a/configs/common/FSConfig.py        Sat Jun 14 21:51:08 2008 -0700
+++ b/configs/common/FSConfig.py        Tue Jun 24 15:51:12 2008 -0400
@@ -68,7 +68,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc
                                                read_only = True))
     self.intrctrl = IntrControl()
     self.mem_mode = mem_mode
-    self.sim_console = SimConsole()
+    self.terminal = Terminal()
     self.kernel = binary('vmlinux')
     self.pal = binary('ts_osfpal')
     self.console = binary('console')
@@ -148,7 +148,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc 
                                                read_only = True))
     self.intrctrl = IntrControl()
     self.mem_mode = mem_mode
-    self.sim_console = SimConsole()
+    self.terminal = Terminal()
     self.kernel = binary('mips/vmlinux')
     self.console = binary('mips/console')
     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
diff -r 47c5168d092c -r d9de38fba64c src/base/inet.hh
--- a/src/base/inet.hh  Sat Jun 14 21:51:08 2008 -0700
+++ b/src/base/inet.hh  Tue Jun 24 15:51:12 2008 -0400
@@ -179,32 +179,31 @@ class IpPtr
     friend class UdpPtr;
     EthPacketPtr p;
 
-    const IpHdr *h() const
-    { return (const IpHdr *)(p->data + sizeof(eth_hdr)); }
-    IpHdr *h() { return (IpHdr *)(p->data + sizeof(eth_hdr)); }
-
     void set(const EthPacketPtr &ptr)
     {
-        EthHdr *eth = (EthHdr *)ptr->data;
-        if (eth->type() == ETH_TYPE_IP)
-            p = ptr;
-        else
-            p = 0;
+        p = 0;
+
+        if (ptr) {
+            EthHdr *eth = (EthHdr *)ptr->data;
+            if (eth->type() == ETH_TYPE_IP)
+                p = ptr;
+        }
     }
 
   public:
-    IpPtr() {}
-    IpPtr(const EthPacketPtr &ptr) { set(ptr); }
-    IpPtr(const EthPtr &ptr) { set(ptr.p); }
+    IpPtr() : p(0) {}
+    IpPtr(const EthPacketPtr &ptr) : p(0) { set(ptr); }
+    IpPtr(const EthPtr &ptr) : p(0) { set(ptr.p); }
     IpPtr(const IpPtr &ptr) : p(ptr.p) { }
 
-    IpHdr *operator->() { return h(); }
-    IpHdr &operator*() { return *h(); }
-    operator IpHdr *() { return h(); }
+    IpHdr *get() { return (IpHdr *)(p->data + sizeof(eth_hdr)); }
+    IpHdr *operator->() { return get(); }
+    IpHdr &operator*() { return *get(); }
 
-    const IpHdr *operator->() const { return h(); }
-    const IpHdr &operator*() const { return *h(); }
-    operator const IpHdr *() const { return h(); }
+    const IpHdr *get() const
+    { return (const IpHdr *)(p->data + sizeof(eth_hdr)); }
+    const IpHdr *operator->() const { return get(); }
+    const IpHdr &operator*() const { return *get(); }
 
     const IpPtr &operator=(const EthPacketPtr &ptr) { set(ptr); return *this; }
     const IpPtr &operator=(const EthPtr &ptr) { set(ptr.p); return *this; }
@@ -214,7 +213,6 @@ class IpPtr
     EthPacketPtr packet() { return p; }
     bool operator!() const { return !p; }
     operator bool() const { return p; }
-    operator bool() { return p; }
 };
 
 uint16_t cksum(const IpPtr &ptr);
@@ -278,30 +276,27 @@ class TcpPtr
     EthPacketPtr p;
     int off;
 
-    const TcpHdr *h() const { return (const TcpHdr *)(p->data + off); }
-    TcpHdr *h() { return (TcpHdr *)(p->data + off); }
-
     void set(const EthPacketPtr &ptr, int offset) { p = ptr; off = offset; }
     void set(const IpPtr &ptr)
     {
-        if (ptr->proto() == IP_PROTO_TCP)
+        if (ptr && ptr->proto() == IP_PROTO_TCP)
             set(ptr.p, sizeof(eth_hdr) + ptr->hlen());
         else
             set(0, 0);
     }
 
   public:
-    TcpPtr() {}
-    TcpPtr(const IpPtr &ptr) { set(ptr); }
+    TcpPtr() : p(0), off(0) {}
+    TcpPtr(const IpPtr &ptr) : p(0), off(0) { set(ptr); }
     TcpPtr(const TcpPtr &ptr) : p(ptr.p), off(ptr.off) {}
 
-    TcpHdr *operator->() { return h(); }
-    TcpHdr &operator*() { return *h(); }
-    operator TcpHdr *() { return h(); }
+    TcpHdr *get() { return (TcpHdr *)(p->data + off); }
+    TcpHdr *operator->() { return get(); }
+    TcpHdr &operator*() { return *get(); }
 
-    const TcpHdr *operator->() const { return h(); }
-    const TcpHdr &operator*() const { return *h(); }
-    operator const TcpHdr *() const { return h(); }
+    const TcpHdr *get() const { return (const TcpHdr *)(p->data + off); }
+    const TcpHdr *operator->() const { return get(); }
+    const TcpHdr &operator*() const { return *get(); }
 
     const TcpPtr &operator=(const IpPtr &i) { set(i); return *this; }
     const TcpPtr &operator=(const TcpPtr &t) { set(t.p, t.off); return *this; }
@@ -310,7 +305,6 @@ class TcpPtr
     EthPacketPtr packet() { return p; }
     bool operator!() const { return !p; }
     operator bool() const { return p; }
-    operator bool() { return p; }
 };
 
 uint16_t cksum(const TcpPtr &ptr);
@@ -368,30 +362,27 @@ class UdpPtr
     EthPacketPtr p;
     int off;
 
-    const UdpHdr *h() const { return (const UdpHdr *)(p->data + off); }
-    UdpHdr *h() { return (UdpHdr *)(p->data + off); }
-
     void set(const EthPacketPtr &ptr, int offset) { p = ptr; off = offset; }
     void set(const IpPtr &ptr)
     {
-        if (ptr->proto() == IP_PROTO_UDP)
+        if (ptr && ptr->proto() == IP_PROTO_UDP)
             set(ptr.p, sizeof(eth_hdr) + ptr->hlen());
         else
             set(0, 0);
     }
 
   public:
-    UdpPtr() {}
-    UdpPtr(const IpPtr &ptr) { set(ptr); }
+    UdpPtr() : p(0), off(0) {}
+    UdpPtr(const IpPtr &ptr) : p(0), off(0) { set(ptr); }
     UdpPtr(const UdpPtr &ptr) : p(ptr.p), off(ptr.off) {}
 
-    UdpHdr *operator->() { return h(); }
-    UdpHdr &operator*() { return *h(); }
-    operator UdpHdr *() { return h(); }
+    UdpHdr *get() { return (UdpHdr *)(p->data + off); }
+    UdpHdr *operator->() { return get(); }
+    UdpHdr &operator*() { return *get(); }
 
-    const UdpHdr *operator->() const { return h(); }
-    const UdpHdr &operator*() const { return *h(); }
-    operator const UdpHdr *() const { return h(); }
+    const UdpHdr *get() const { return (const UdpHdr *)(p->data + off); }
+    const UdpHdr *operator->() const { return get(); }
+    const UdpHdr &operator*() const { return *get(); }
 
     const UdpPtr &operator=(const IpPtr &i) { set(i); return *this; }
     const UdpPtr &operator=(const UdpPtr &t) { set(t.p, t.off); return *this; }
@@ -400,7 +391,6 @@ class UdpPtr
     EthPacketPtr packet() { return p; }
     bool operator!() const { return !p; }
     operator bool() const { return p; }
-    operator bool() { return p; }
 };
 
 uint16_t cksum(const UdpPtr &ptr);
diff -r 47c5168d092c -r d9de38fba64c src/cpu/base.cc
--- a/src/cpu/base.cc   Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/base.cc   Tue Jun 24 15:51:12 2008 -0400
@@ -351,22 +351,17 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, P
     // Connect new CPU to old CPU's memory only if new CPU isn't
     // connected to anything.  Also connect old CPU's memory to new
     // CPU.
-    Port *peer;
-    if (ic->getPeer() == NULL || ic->getPeer()->isDefaultPort()) {
-        peer = oldCPU->getPort("icache_port")->getPeer();
+    if (!ic->isConnected()) {
+        Port *peer = oldCPU->getPort("icache_port")->getPeer();
         ic->setPeer(peer);
-    } else {
-        peer = ic->getPeer();
+        peer->setPeer(ic);
     }
-    peer->setPeer(ic);
 
-    if (dc->getPeer() == NULL || dc->getPeer()->isDefaultPort()) {
-        peer = oldCPU->getPort("dcache_port")->getPeer();
+    if (!dc->isConnected()) {
+        Port *peer = oldCPU->getPort("dcache_port")->getPeer();
         dc->setPeer(peer);
-    } else {
-        peer = dc->getPeer();
+        peer->setPeer(dc);
     }
-    peer->setPeer(dc);
 }
 
 
diff -r 47c5168d092c -r d9de38fba64c src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh       Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/o3/fetch.hh       Tue Jun 24 15:51:12 2008 -0400
@@ -80,8 +80,8 @@ class DefaultFetch
 
       public:
         /** Default constructor. */
-        IcachePort(DefaultFetch<Impl> *_fetch)
-            : Port(_fetch->name() + "-iport"), fetch(_fetch)
+        IcachePort(DefaultFetch<Impl> *_fetch, O3CPU *_cpu)
+            : Port(_fetch->name() + "-iport", _cpu), fetch(_fetch)
         { }
 
         bool snoopRangeSent;
diff -r 47c5168d092c -r d9de38fba64c src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh  Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/o3/fetch_impl.hh  Tue Jun 24 15:51:12 2008 -0400
@@ -167,7 +167,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *
     instSize = sizeof(TheISA::MachInst);
 
     // Name is finally available, so create the port.
-    icachePort = new IcachePort(this);
+    icachePort = new IcachePort(this, cpu);
 
     icachePort->snoopRangeSent = false;
 
diff -r 47c5168d092c -r d9de38fba64c src/cpu/o3/lsq.hh
--- a/src/cpu/o3/lsq.hh Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/o3/lsq.hh Tue Jun 24 15:51:12 2008 -0400
@@ -296,8 +296,8 @@ class LSQ {
 
       public:
         /** Default constructor. */
-        DcachePort(LSQ *_lsq)
-            : Port(_lsq->name() + "-dport"), lsq(_lsq)
+        DcachePort(LSQ *_lsq, O3CPU *_cpu)
+            : Port(_lsq->name() + "-dport", _cpu), lsq(_lsq)
         { }
 
         bool snoopRangeSent;
diff -r 47c5168d092c -r d9de38fba64c src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh    Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/o3/lsq_impl.hh    Tue Jun 24 15:51:12 2008 -0400
@@ -112,7 +112,7 @@ LSQ<Impl>::DcachePort::recvRetry()
 
 template <class Impl>
 LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params)
-    : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
+    : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this, cpu_ptr),
       LQEntries(params->LQEntries),
       SQEntries(params->SQEntries),
       numThreads(params->numberOfThreads),
diff -r 47c5168d092c -r d9de38fba64c src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/o3/thread_context_impl.hh Tue Jun 24 15:51:12 2008 -0400
@@ -103,7 +103,6 @@ O3ThreadContext<Impl>::delVirtPort(Virtu
 O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
 {
     if (vp != thread->getVirtPort()) {
-        vp->removeConn();
         delete vp;
     }
 }
diff -r 47c5168d092c -r d9de38fba64c src/cpu/ozone/cpu_impl.hh
--- a/src/cpu/ozone/cpu_impl.hh Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/ozone/cpu_impl.hh Tue Jun 24 15:51:12 2008 -0400
@@ -747,7 +747,6 @@ void
 void
 OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
 {
-    vp->removeConn();
     delete vp;
 }
 #endif
diff -r 47c5168d092c -r d9de38fba64c src/cpu/simple/AtomicSimpleCPU.py
--- a/src/cpu/simple/AtomicSimpleCPU.py Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/simple/AtomicSimpleCPU.py Tue Jun 24 15:51:12 2008 -0400
@@ -33,7 +33,8 @@ class AtomicSimpleCPU(BaseCPU):
 class AtomicSimpleCPU(BaseCPU):
     type = 'AtomicSimpleCPU'
     width = Param.Int(1, "CPU width")
-    simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
+    simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
+    simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
     if build_env['FULL_SYSTEM']:
diff -r 47c5168d092c -r d9de38fba64c src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc  Sat Jun 14 21:51:08 2008 -0700
+++ b/src/cpu/simple/atomic.cc  Tue Jun 24 15:51:12 2008 -0400
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Reply via email to