changeset d8ab33f5ff9a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d8ab33f5ff9a
description:
Return an UnimpFault for an ITB translation of an uncachable address.
We don't support fetching from uncached addresses in Alpha and it means that a
speculative fetch can clobber device registers.
diffstat:
0 files changed
diffs (46 lines):
diff -r a5ff5e57fafd -r d8ab33f5ff9a src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Mon Aug 11 14:47:49 2008 -0700
+++ b/src/arch/alpha/tlb.cc Wed Aug 13 16:29:59 2008 -0400
@@ -116,7 +116,7 @@
Fault
-TLB::checkCacheability(RequestPtr &req)
+TLB::checkCacheability(RequestPtr &req, bool itb)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
@@ -148,6 +148,12 @@
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
#endif
}
+ // We shouldn't be able to read from an uncachable address in Alpha as
+ // we don't have a ROM and we don't want to try to fetch from a device
+ // register as we destroy any data that is clear-on-read.
+ if (req->isUncacheable() && itb)
+ return new UnimpFault("CPU trying to fetch from uncached I/O");
+
}
return NoFault;
}
@@ -390,7 +396,7 @@
if (req->getPaddr() & ~PAddrImplMask)
return genMachineCheckFault();
- return checkCacheability(req);
+ return checkCacheability(req, true);
}
diff -r a5ff5e57fafd -r d8ab33f5ff9a src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Mon Aug 11 14:47:49 2008 -0700
+++ b/src/arch/alpha/tlb.hh Wed Aug 13 16:29:59 2008 -0400
@@ -92,7 +92,7 @@
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
}
- static Fault checkCacheability(RequestPtr &req);
+ static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
virtual void serialize(std::ostream &os);
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