changeset 92b89377be48 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=92b89377be48
description:
More subtle fixes to how interrupts are supposed to work in the device.
Fix postedInterrupts statistics.
diffstat:
0 files changed
diffs (59 lines):
diff -r d8ab33f5ff9a -r 92b89377be48 src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc Wed Aug 13 16:29:59 2008 -0400
+++ b/src/dev/i8254xGBe.cc Wed Aug 13 16:30:30 2008 -0400
@@ -588,7 +588,6 @@
if (interEvent.scheduled()) {
interEvent.deschedule();
}
- postedInterrupts++;
cpuPostInt();
} else {
Tick int_time = lastInterrupt + itr_interval;
@@ -611,6 +610,8 @@
void
IGbE::cpuPostInt()
{
+
+ postedInterrupts++;
if (!(regs.icr() & regs.imr)) {
DPRINTF(Ethernet, "Interrupt Masked. Not Posting\n");
diff -r d8ab33f5ff9a -r 92b89377be48 src/dev/i8254xGBe.hh
--- a/src/dev/i8254xGBe.hh Wed Aug 13 16:29:59 2008 -0400
+++ b/src/dev/i8254xGBe.hh Wed Aug 13 16:30:30 2008 -0400
@@ -87,7 +87,7 @@
void rdtrProcess() {
rxDescCache.writeback(0);
DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer
expired\n");
- postInterrupt(iGbReg::IT_RXT, true);
+ postInterrupt(iGbReg::IT_RXT);
}
//friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
@@ -97,7 +97,7 @@
void radvProcess() {
rxDescCache.writeback(0);
DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer
expired\n");
- postInterrupt(iGbReg::IT_RXT, true);
+ postInterrupt(iGbReg::IT_RXT);
}
//friend class EventWrapper<IGbE, &IGbE::radvProcess>;
@@ -107,7 +107,7 @@
void tadvProcess() {
txDescCache.writeback(0);
DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer
expired\n");
- postInterrupt(iGbReg::IT_TXDW, true);
+ postInterrupt(iGbReg::IT_TXDW);
}
//friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
@@ -117,7 +117,7 @@
void tidvProcess() {
txDescCache.writeback(0);
DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer
expired\n");
- postInterrupt(iGbReg::IT_TXDW, true);
+ postInterrupt(iGbReg::IT_TXDW);
}
//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
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