changeset cdc8893c649e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cdc8893c649e
description:
O3: Generaize the O3 dynamic instruction class so it isn't split out by
ISA.
diffstat:
15 files changed, 121 insertions(+), 648 deletions(-)
src/arch/mips/locked_mem.hh | 3
src/cpu/o3/alpha/dyn_inst.cc | 1
src/cpu/o3/alpha/dyn_inst.hh | 138 ------------------------------------
src/cpu/o3/alpha/dyn_inst_impl.hh | 87 ----------------------
src/cpu/o3/dyn_inst.hh | 2
src/cpu/o3/dyn_inst_decl.hh | 28 +++++++
src/cpu/o3/dyn_inst_impl.hh | 90 +++++++++++++++++++++++
src/cpu/o3/isa_specific.hh | 1
src/cpu/o3/mips/dyn_inst.cc | 2
src/cpu/o3/mips/dyn_inst.hh | 140 -------------------------------------
src/cpu/o3/mips/dyn_inst_impl.hh | 65 -----------------
src/cpu/o3/mips/impl.hh | 1
src/cpu/o3/sparc/dyn_inst.cc | 2
src/cpu/o3/sparc/dyn_inst.hh | 132 ----------------------------------
src/cpu/o3/sparc/dyn_inst_impl.hh | 77 --------------------
diffs (truncated from 2050 to 300 lines):
diff -r 6ebdae3f619b -r cdc8893c649e src/arch/mips/locked_mem.hh
--- a/src/arch/mips/locked_mem.hh Thu Oct 09 00:08:50 2008 -0700
+++ b/src/arch/mips/locked_mem.hh Thu Oct 09 00:09:26 2008 -0700
@@ -49,11 +49,10 @@
inline void
handleLockedRead(XC *xc, Request *req)
{
- unsigned tid = req->getThreadNum();
- xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid);
- xc->setMiscRegNoEffect(LLFlag, true, tid);
+ xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
+ xc->setMiscRegNoEffect(LLFlag, true);
DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to
%x.\n",
- tid, req->getPaddr() & ~0xf);
+ req->getThreadNum(), req->getPaddr() & ~0xf);
}
@@ -61,22 +60,20 @@
inline bool
handleLockedWrite(XC *xc, Request *req)
{
- unsigned tid = req->getThreadNum();
-
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
// result register (see stq_c in decoder.isa)
req->setExtraData(2);
} else {
// standard store conditional
- bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid);
- Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid);
+ bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
+ Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
req->setExtraData(0);
- xc->setMiscRegNoEffect(LLFlag, false, tid);
+ xc->setMiscRegNoEffect(LLFlag, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect
@@ -97,10 +94,10 @@
if (!lock_flag){
DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional
Failed.\n",
- tid);
+ req->getThreadNum());
} else if ((req->getPaddr() & ~0xf) != lock_addr) {
DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store
Conditional Failed.\n",
- tid);
+ req->getThreadNum());
}
// store conditional failed already, so don't issue it to mem
return false;
diff -r 6ebdae3f619b -r cdc8893c649e src/cpu/o3/alpha/dyn_inst.cc
--- a/src/cpu/o3/alpha/dyn_inst.cc Thu Oct 09 00:08:50 2008 -0700
+++ b/src/cpu/o3/alpha/dyn_inst.cc Thu Oct 09 00:09:26 2008 -0700
@@ -28,9 +28,9 @@
* Authors: Kevin Lim
*/
-#include "cpu/o3/alpha/dyn_inst_impl.hh"
#include "cpu/o3/alpha/impl.hh"
+#include "cpu/o3/dyn_inst_impl.hh"
// Force instantiation of AlphaDynInst for all the implementations that
// are needed.
-template class AlphaDynInst<AlphaSimpleImpl>;
+template class BaseO3DynInst<AlphaSimpleImpl>;
diff -r 6ebdae3f619b -r cdc8893c649e src/cpu/o3/alpha/dyn_inst.hh
--- a/src/cpu/o3/alpha/dyn_inst.hh Thu Oct 09 00:08:50 2008 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,277 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_ALPHA_DYN_INST_HH__
-#define __CPU_O3_ALPHA_DYN_INST_HH__
-
-#include "arch/isa_traits.hh"
-#include "cpu/base_dyn_inst.hh"
-#include "cpu/inst_seq.hh"
-#include "cpu/o3/alpha/impl.hh"
-#include "cpu/o3/cpu.hh"
-
-class Packet;
-
-/**
- * Mostly implementation & ISA specific AlphaDynInst. As with most
- * other classes in the new CPU model, it is templated on the Impl to
- * allow for passing in of all types, such as the CPU type and the ISA
- * type. The AlphaDynInst serves as the primary interface to the CPU
- * for instructions that are executing.
- */
-template <class Impl>
-class AlphaDynInst : public BaseDynInst<Impl>
-{
- public:
- /** Typedef for the CPU. */
- typedef typename Impl::O3CPU O3CPU;
-
- /** Binary machine instruction type. */
- typedef TheISA::MachInst MachInst;
- /** Extended machine instruction type. */
- typedef TheISA::ExtMachInst ExtMachInst;
- /** Logical register index type. */
- typedef TheISA::RegIndex RegIndex;
- /** Integer register index type. */
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- /** Misc register index type. */
- typedef TheISA::MiscReg MiscReg;
-
- enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
- };
-
- public:
- /** BaseDynInst constructor given a binary instruction. */
- AlphaDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
- Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
- InstSeqNum seq_num, O3CPU *cpu);
-
- /** BaseDynInst constructor given a binary instruction. */
- AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
- Addr Pred_PC, Addr Pred_NPC, Addr Pred_MicroPC,
- InstSeqNum seq_num, O3CPU *cpu);
-
- /** BaseDynInst constructor given a static inst pointer. */
- AlphaDynInst(StaticInstPtr &_staticInst);
-
- /** Executes the instruction.*/
- Fault execute();
-
- /** Initiates the access. Only valid for memory operations. */
- Fault initiateAcc();
-
- /** Completes the access. Only valid for memory operations. */
- Fault completeAcc(PacketPtr pkt);
-
- private:
- /** Initializes variables. */
- void initVars();
-
- public:
- /** Reads a miscellaneous register. */
- MiscReg readMiscRegNoEffect(int misc_reg)
- {
- return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber);
- }
-
- /** Reads a misc. register, including any side-effects the read
- * might have as defined by the architecture.
- */
- MiscReg readMiscReg(int misc_reg)
- {
- return this->cpu->readMiscReg(misc_reg, this->threadNumber);
- }
-
- /** Sets a misc. register. */
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- {
- this->instResult.integer = val;
- return this->cpu->setMiscRegNoEffect(misc_reg, val,
this->threadNumber);
- }
-
- /** Sets a misc. register, including any side-effects the write
- * might have as defined by the architecture.
- */
- void setMiscReg(int misc_reg, const MiscReg &val)
- {
- return this->cpu->setMiscReg(misc_reg, val,
- this->threadNumber);
- }
-
- /** Reads a miscellaneous register. */
- TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
- {
- return this->cpu->readMiscRegNoEffect(
- si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- this->threadNumber);
- }
-
- /** Reads a misc. register, including any side-effects the read
- * might have as defined by the architecture.
- */
- TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
- {
- return this->cpu->readMiscReg(
- si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- this->threadNumber);
- }
-
- /** Sets a misc. register. */
- void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const
MiscReg &val)
- {
- this->instResult.integer = val;
- return this->cpu->setMiscRegNoEffect(
- si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- val, this->threadNumber);
- }
-
- /** Sets a misc. register, including any side-effects the write
- * might have as defined by the architecture.
- */
- void setMiscRegOperand(const StaticInst *si, int idx,
- const MiscReg &val)
- {
- return this->cpu->setMiscReg(
- si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- val, this->threadNumber);
- }
-
-#if FULL_SYSTEM
- /** Calls hardware return from error interrupt. */
- Fault hwrei();
- /** Traps to handle specified fault. */
- void trap(Fault fault);
- bool simPalCheck(int palFunc);
-#else
- /** Calls a syscall. */
- void syscall(int64_t callnum);
-#endif
-
- public:
-
- // The register accessor methods provide the index of the
- // instruction's operand (e.g., 0 or 1), not the architectural
- // register index, to simplify the implementation of register
- // renaming. We find the architectural register index by indexing
- // into the instruction's own operand index table. Note that a
- // raw pointer to the StaticInst is provided instead of a
- // ref-counted StaticInstPtr to redice overhead. This is fine as
- // long as these methods don't copy the pointer into any long-term
- // storage (which is pretty hard to imagine they would have reason
- // to do).
-
- uint64_t readIntRegOperand(const StaticInst *si, int idx)
- {
- return this->cpu->readIntReg(this->_srcRegIdx[idx]);
- }
-
- FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
- {
- return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
- }
-
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
- {
- return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
- }
-
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
- int width)
- {
- return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
- }
-
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
- {
- return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
- }
-
- /** @todo: Make results into arrays so they can handle multiple dest
- * registers.
- */
- void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
- {
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