changeset e2983d751be4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e2983d751be4
description:
O3: Generaize the O3 IMPL class so it isn't split out by ISA.
diffstat:
22 files changed, 118 insertions(+), 442 deletions(-)
src/cpu/o3/SConscript | 1
src/cpu/o3/alpha/cpu.cc | 18 --------------
src/cpu/o3/alpha/cpu_builder.cc | 39 -------------------------------
src/cpu/o3/alpha/dyn_inst.cc | 18 --------------
src/cpu/o3/alpha/impl.hh | 44 ------------------------------------
src/cpu/o3/alpha/thread_context.cc | 18 --------------
src/cpu/o3/cpu_builder.cc | 39 +++++++++++++++++++++++++++++++
src/cpu/o3/dyn_inst.cc | 18 ++++++++++++++
src/cpu/o3/dyn_inst_decl.hh | 28 ----------------------
src/cpu/o3/impl.hh | 42 ++++++++++++++++++++++++++++++++++
src/cpu/o3/isa_specific.hh | 3 --
src/cpu/o3/mips/cpu.cc | 19 ---------------
src/cpu/o3/mips/cpu_builder.cc | 39 -------------------------------
src/cpu/o3/mips/dyn_inst.cc | 18 --------------
src/cpu/o3/mips/impl.hh | 44 ------------------------------------
src/cpu/o3/mips/thread_context.cc | 18 --------------
src/cpu/o3/sparc/cpu.cc | 18 --------------
src/cpu/o3/sparc/cpu_builder.cc | 39 -------------------------------
src/cpu/o3/sparc/dyn_inst.cc | 18 --------------
src/cpu/o3/sparc/impl.hh | 44 ------------------------------------
src/cpu/o3/sparc/thread_context.cc | 17 -------------
src/cpu/o3/thread_context.cc | 18 ++++++++++++++
diffs (truncated from 1284 to 300 lines):
diff -r cdc8893c649e -r e2983d751be4 src/cpu/o3/SConscript
--- a/src/cpu/o3/SConscript Thu Oct 09 00:09:26 2008 -0700
+++ b/src/cpu/o3/SConscript Thu Oct 09 00:10:02 2008 -0700
@@ -51,7 +51,9 @@
Source('bpred_unit.cc')
Source('commit.cc')
Source('cpu.cc')
+ Source('cpu_builder.cc')
Source('decode.cc')
+ Source('dyn_inst.cc')
Source('fetch.cc')
Source('free_list.cc')
Source('fu_pool.cc')
@@ -65,6 +67,7 @@
Source('rob.cc')
Source('scoreboard.cc')
Source('store_set.cc')
+ Source('thread_context.cc')
TraceFlag('FreeList')
TraceFlag('LSQ')
@@ -81,24 +84,6 @@
'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
- if env['TARGET_ISA'] == 'alpha':
- Source('alpha/cpu.cc')
- Source('alpha/cpu_builder.cc')
- Source('alpha/dyn_inst.cc')
- Source('alpha/thread_context.cc')
- elif env['TARGET_ISA'] == 'mips':
- Source('mips/cpu.cc')
- Source('mips/cpu_builder.cc')
- Source('mips/dyn_inst.cc')
- Source('mips/thread_context.cc')
- elif env['TARGET_ISA'] == 'sparc':
- Source('sparc/cpu.cc')
- Source('sparc/cpu_builder.cc')
- Source('sparc/dyn_inst.cc')
- Source('sparc/thread_context.cc')
- else:
- sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
-
if env['USE_CHECKER']:
SimObject('O3Checker.py')
Source('checker_builder.cc')
diff -r cdc8893c649e -r e2983d751be4 src/cpu/o3/alpha/cpu.cc
--- a/src/cpu/o3/alpha/cpu.cc Thu Oct 09 00:09:26 2008 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include "cpu/o3/alpha/impl.hh"
-#include "cpu/o3/cpu.hh"
-
-// Force instantiation of AlphaO3CPU for all the implemntations that are
-// needed. Consider merging this and alpha_dyn_inst.cc, and maybe all
-// classes that depend on a certain impl, into one file (alpha_impl.cc?).
-template class FullO3CPU<AlphaSimpleImpl>;
diff -r cdc8893c649e -r e2983d751be4 src/cpu/o3/alpha/cpu_builder.cc
--- a/src/cpu/o3/alpha/cpu_builder.cc Thu Oct 09 00:09:26 2008 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include <string>
-
-#include "config/full_system.hh"
-#include "config/use_checker.hh"
-#include "cpu/o3/cpu.hh"
-#include "cpu/o3/alpha/impl.hh"
-#include "params/DerivO3CPU.hh"
-
-class DerivO3CPU : public FullO3CPU<AlphaSimpleImpl>
-{
- public:
- DerivO3CPU(DerivO3CPUParams *p)
- : FullO3CPU<AlphaSimpleImpl>(p)
- { }
-};
-
-DerivO3CPU *
-DerivO3CPUParams::create()
-{
-#if FULL_SYSTEM
- // Full-system only supports a single thread for the moment.
- int actual_num_threads = 1;
-#else
- // In non-full-system mode, we infer the number of threads from
- // the workload if it's not explicitly specified.
- int actual_num_threads =
- (numThreads >= workload.size()) ? numThreads : workload.size();
-
- if (workload.size() == 0) {
- fatal("Must specify at least one workload!");
- }
-#endif
-
- numThreads = actual_num_threads;
-
- // Default smtFetchPolicy to "RoundRobin", if necessary.
- std::string round_robin_policy = "RoundRobin";
- std::string single_thread = "SingleThread";
-
- if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
- smtFetchPolicy = round_robin_policy;
- else
- smtFetchPolicy = smtFetchPolicy;
-
- instShiftAmt = 2;
-
- return new DerivO3CPU(this);
-}
diff -r cdc8893c649e -r e2983d751be4 src/cpu/o3/alpha/dyn_inst.cc
--- a/src/cpu/o3/alpha/dyn_inst.cc Thu Oct 09 00:09:26 2008 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#include "cpu/o3/alpha/impl.hh"
-#include "cpu/o3/dyn_inst_impl.hh"
-
-// Force instantiation of AlphaDynInst for all the implementations that
-// are needed.
-template class BaseO3DynInst<AlphaSimpleImpl>;
diff -r cdc8893c649e -r e2983d751be4 src/cpu/o3/alpha/impl.hh
--- a/src/cpu/o3/alpha/impl.hh Thu Oct 09 00:09:26 2008 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_O3_ALPHA_IMPL_HH__
-#define __CPU_O3_ALPHA_IMPL_HH__
-
-#include "arch/alpha/isa_traits.hh"
-
-#include "cpu/o3/cpu_policy.hh"
-
-
-// Forward declarations.
-template <class Impl>
-class BaseO3DynInst;
-
-template <class Impl>
-class FullO3CPU;
-
-/** Implementation specific struct that defines several key types to the
- * CPU, the stages within the CPU, the time buffers, and the DynInst.
- * The struct defines the ISA, the CPU policy, the specific DynInst, the
- * specific O3CPU, and all of the structs from the time buffers to do
- * communication.
- * This is one of the key things that must be defined for each hardware
- * specific CPU implementation.
- */
-struct AlphaSimpleImpl
-{
- /** The type of MachInst. */
- typedef TheISA::MachInst MachInst;
-
- /** The CPU policy to be used, which defines all of the CPU stages. */
- typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
-
- /** The DynInst type to be used. */
- typedef BaseO3DynInst<AlphaSimpleImpl> DynInst;
-
- /** The refcounted DynInst pointer to be used. In most cases this is
- * what should be used, and not DynInst *.
- */
- typedef RefCountingPtr<DynInst> DynInstPtr;
-
- /** The O3CPU type to be used. */
- typedef FullO3CPU<AlphaSimpleImpl> O3CPU;
-
- /** Same typedef, but for CPUType. BaseDynInst may not always use
- * an O3 CPU, so it's clearer to call it CPUType instead in that
- * case.
- */
- typedef O3CPU CPUType;
-
- enum {
- MaxWidth = 8,
- MaxThreads = 4
- };
-};
-
-/** The O3Impl to be used. */
-typedef AlphaSimpleImpl O3CPUImpl;
-
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