changeset 0a488a147fb8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0a488a147fb8
description:
CPU: Eliminate the get_vec function.
diffstat:
6 files changed, 6 insertions(+), 14 deletions(-)
src/arch/alpha/interrupts.hh | 3 ---
src/arch/mips/interrupts.cc | 3 ---
src/arch/mips/interrupts.hh | 1 -
src/arch/sparc/tlb.cc | 7 ++++++-
src/arch/x86/interrupts.hh | 3 ---
src/cpu/base.cc | 3 ---
diffs (162 lines):
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/arch/alpha/interrupts.hh
--- a/src/arch/alpha/interrupts.hh Sat Oct 11 16:13:58 2008 -0700
+++ b/src/arch/alpha/interrupts.hh Sun Oct 12 08:24:09 2008 -0700
@@ -171,13 +171,6 @@
tc->setMiscRegNoEffect(IPR_INTID, newIpl);
newInfoSet = false;
}
-
- uint64_t
- get_vec(int int_num)
- {
- panic("Shouldn't be called for Alpha\n");
- M5_DUMMY_RETURN;
- }
};
} // namespace AlphaISA
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/arch/mips/interrupts.cc
--- a/src/arch/mips/interrupts.cc Sat Oct 11 16:13:58 2008 -0700
+++ b/src/arch/mips/interrupts.cc Sun Oct 12 08:24:09 2008 -0700
@@ -156,12 +156,6 @@
return false;
}
-
- uint64_t Interrupts::get_vec(int int_num)
- {
- panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
- M5_DUMMY_RETURN
- }
*/
void Interrupts::post(int int_num, ThreadContext* tc)
{
@@ -252,12 +246,6 @@
;
}
-uint64_t Interrupts::get_vec(int int_num)
-{
- panic("MipsISA::Interrupts::get_vec() is not implemented. \n");
- M5_DUMMY_RETURN
- }
-
bool Interrupts::interruptsPending(ThreadContext *tc) const
{
//if there is a on cpu timer interrupt (i.e. Compare == Count)
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/arch/mips/interrupts.hh
--- a/src/arch/mips/interrupts.hh Sat Oct 11 16:13:58 2008 -0700
+++ b/src/arch/mips/interrupts.hh Sun Oct 12 08:24:09 2008 -0700
@@ -91,8 +91,6 @@
void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
- uint64_t get_vec(int int_num);
-
bool check_interrupts(ThreadContext * tc) const{
//return (intstatus != 0) && !(tc->readPC() & 0x3);
if (oncputimerintr == false){
@@ -160,8 +158,6 @@
bool interruptsPending(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
- uint64_t get_vec(int int_num);
-
bool check_interrupts(ThreadContext * tc) const{
return interruptsPending(tc);
}
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Sat Oct 11 16:13:58 2008 -0700
+++ b/src/arch/sparc/tlb.cc Sun Oct 12 08:24:09 2008 -0700
@@ -1008,12 +1008,22 @@
itb->cx_config));
break;
case ASI_SWVR_INTR_RECEIVE:
- pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
+ {
+ SparcISA::Interrupts * interrupts =
+ dynamic_cast<SparcISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController());
+ pkt->set(interrupts->get_vec(IT_INT_VEC));
+ }
break;
case ASI_SWVR_UDB_INTR_R:
- temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
- tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
- pkt->set(temp);
+ {
+ SparcISA::Interrupts * interrupts =
+ dynamic_cast<SparcISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController());
+ temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
+ tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
+ pkt->set(temp);
+ }
break;
default:
doMmuReadError:
@@ -1252,11 +1262,16 @@
}
break;
case ASI_SWVR_INTR_RECEIVE:
- int msb;
- // clear all the interrupts that aren't set in the write
- while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
- msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) &
data);
- tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+ {
+ int msb;
+ // clear all the interrupts that aren't set in the write
+ SparcISA::Interrupts * interrupts =
+ dynamic_cast<SparcISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController());
+ while(interrupts->get_vec(IT_INT_VEC) & data) {
+ msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
+ tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+ }
}
break;
case ASI_SWVR_UDB_INTR_W:
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh Sat Oct 11 16:13:58 2008 -0700
+++ b/src/arch/x86/interrupts.hh Sun Oct 12 08:24:09 2008 -0700
@@ -108,12 +108,6 @@
panic("Interrupts::updateIntrInfo unimplemented!\n");
}
- uint64_t get_vec(int int_num)
- {
- panic("Interrupts::get_vec unimplemented!\n");
- return 0;
- }
-
void serialize(std::ostream & os)
{
panic("Interrupts::serialize unimplemented!\n");
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/cpu/base.cc
--- a/src/cpu/base.cc Sat Oct 11 16:13:58 2008 -0700
+++ b/src/cpu/base.cc Sun Oct 12 08:24:09 2008 -0700
@@ -396,12 +396,6 @@
interrupts.clear_all();
}
-uint64_t
-BaseCPU::get_interrupts(int int_num)
-{
- return interrupts.get_vec(int_num);
-}
-
void
BaseCPU::serialize(std::ostream &os)
{
diff -r 0d35ed236aa1 -r 0a488a147fb8 src/cpu/base.hh
--- a/src/cpu/base.hh Sat Oct 11 16:13:58 2008 -0700
+++ b/src/cpu/base.hh Sun Oct 12 08:24:09 2008 -0700
@@ -119,7 +119,6 @@
virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts();
- virtual uint64_t get_interrupts(int int_num);
bool check_interrupts(ThreadContext * tc) const
{ return interrupts.check_interrupts(tc); }
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