changeset b06b49498c79 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b06b49498c79
description:
Turn Interrupts objects into SimObjects. Also, move local APIC state
into x86's Interrupts object.
diffstat:
23 files changed, 306 insertions(+), 16 deletions(-)
src/arch/alpha/AlphaInterrupts.py | 16 +++++
src/arch/alpha/SConscript | 1
src/arch/alpha/interrupts.cc | 18 +++++
src/arch/alpha/interrupts.hh | 3
src/arch/mips/MipsInterrupts.py | 16 +++++
src/arch/sparc/SConscript | 1
src/arch/sparc/SparcInterrupts.py | 16 +++++
src/arch/sparc/interrupts.cc | 18 +++++
src/arch/sparc/interrupts.hh | 2
src/arch/x86/SConscript | 1
src/arch/x86/X86LocalApic.py | 17 +++++
src/arch/x86/apicregs.hh | 45 ++++++++++++++
src/arch/x86/interrupts.cc | 113 +++++++++++++++++++++++++++++++++++++
src/arch/x86/interrupts.hh | 19 +++++-
src/arch/x86/miscregfile.cc | 5 -
src/arch/x86/mmaped_ipr.hh | 3
src/arch/x86/regfile.cc | 4 -
src/arch/x86/tlb.cc | 8 +-
src/arch/x86/utility.cc | 5 +
src/cpu/BaseCPU.py | 5 +
src/cpu/base.hh | 2
src/cpu/ozone/cpu_impl.hh | 2
src/cpu/simple/base.cc | 2
diffs (truncated from 1519 to 300 lines):
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/alpha/AlphaInterrupts.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/alpha/AlphaInterrupts.py Sun Oct 12 09:09:56 2008 -0700
@@ -0,0 +1,33 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class AlphaInterrupts(SimObject):
+ type = 'AlphaInterrupts'
+ cxx_class = 'AlphaISA::Interrupts'
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript Sun Oct 12 08:24:09 2008 -0700
+++ b/src/arch/alpha/SConscript Sun Oct 12 09:09:56 2008 -0700
@@ -47,9 +47,11 @@
SimObject('AlphaTLB.py')
if env['FULL_SYSTEM']:
+ SimObject('AlphaInterrupts.py')
SimObject('AlphaSystem.py')
Source('idle_event.cc')
+ Source('interrupts.cc')
Source('kernel_stats.cc')
Source('osfpal.cc')
Source('stacktrace.cc')
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/alpha/interrupts.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/alpha/interrupts.cc Sun Oct 12 09:09:56 2008 -0700
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/alpha/interrupts.hh"
+
+AlphaISA::Interrupts *
+AlphaInterruptsParams::create()
+{
+ return new AlphaISA::Interrupts(this);
+}
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/alpha/interrupts.hh
--- a/src/arch/alpha/interrupts.hh Sun Oct 12 08:24:09 2008 -0700
+++ b/src/arch/alpha/interrupts.hh Sun Oct 12 09:09:56 2008 -0700
@@ -35,11 +35,14 @@
#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/compiler.hh"
+#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "params/AlphaInterrupts.hh"
+#include "sim/sim_object.hh"
namespace AlphaISA {
-class Interrupts
+class Interrupts : public SimObject
{
private:
bool newInfoSet;
@@ -51,7 +54,15 @@
uint64_t intstatus;
public:
- Interrupts()
+ typedef AlphaInterruptsParams Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ Interrupts(Params * p) : SimObject(p)
{
memset(interrupts, 0, sizeof(interrupts));
intstatus = 0;
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/mips/MipsInterrupts.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/mips/MipsInterrupts.py Sun Oct 12 09:09:56 2008 -0700
@@ -0,0 +1,33 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class MipsInterrupts(SimObject):
+ type = 'MipsInterrupts'
+ cxx_class = 'MipsISA::Interrupts'
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/mips/SConscript
--- a/src/arch/mips/SConscript Sun Oct 12 08:24:09 2008 -0700
+++ b/src/arch/mips/SConscript Sun Oct 12 09:09:56 2008 -0700
@@ -51,6 +51,7 @@
if env['FULL_SYSTEM']:
SimObject('MipsSystem.py')
+ SimObject('MipsInterrupts.py')
Source('idle_event.cc')
Source('mips_core_specific.cc')
Source('vtophys.cc')
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/sparc/SConscript
--- a/src/arch/sparc/SConscript Sun Oct 12 08:24:09 2008 -0700
+++ b/src/arch/sparc/SConscript Sun Oct 12 09:09:56 2008 -0700
@@ -52,7 +52,9 @@
if env['FULL_SYSTEM']:
SimObject('SparcSystem.py')
+ SimObject('SparcInterrupts.py')
+ Source('interrupts.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('ua2005.cc')
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/sparc/SparcInterrupts.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/sparc/SparcInterrupts.py Sun Oct 12 09:09:56 2008 -0700
@@ -0,0 +1,33 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class SparcInterrupts(SimObject):
+ type = 'SparcInterrupts'
+ cxx_class = 'SparcISA::Interrupts'
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/sparc/interrupts.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/sparc/interrupts.cc Sun Oct 12 09:09:56 2008 -0700
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/interrupts.hh"
+
+SparcISA::Interrupts *
+SparcInterruptsParams::create()
+{
+ return new SparcISA::Interrupts(this);
+}
diff -r 0a488a147fb8 -r b06b49498c79 src/arch/sparc/interrupts.hh
--- a/src/arch/sparc/interrupts.hh Sun Oct 12 08:24:09 2008 -0700
+++ b/src/arch/sparc/interrupts.hh Sun Oct 12 09:09:56 2008 -0700
@@ -35,11 +35,13 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
#include "cpu/thread_context.hh"
+#include "params/SparcInterrupts.hh"
+#include "sim/sim_object.hh"
namespace SparcISA
{
-class Interrupts
+class Interrupts : public SimObject
{
private:
@@ -48,7 +50,15 @@
uint64_t intStatus;
public:
- Interrupts()
+ typedef SparcInterruptsParams Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ Interrupts(Params * p) : SimObject(p)
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