changeset 55f9947891fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=55f9947891fb
description:
X86: Fix the ordering of special physical address ranges.
diffstat:
1 file changed, 1 deletion(-)
src/arch/x86/x86_traits.hh | 1 -
diffs (26 lines):
diff -r 7539092b28ac -r 55f9947891fb src/arch/x86/x86_traits.hh
--- a/src/arch/x86/x86_traits.hh Sun Oct 12 13:54:57 2008 -0700
+++ b/src/arch/x86/x86_traits.hh Sun Oct 12 14:01:06 2008 -0700
@@ -92,8 +92,8 @@
const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
- const Addr PhysAddrPrefixLocalAPIC = ULL(0xA000000000000000);
- const Addr PhysAddrPrefixInterrupts = ULL(0x2000000000000000);
+ const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000);
+ const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000);
// Each APIC gets two pages. One page is used for local apics to field
// accesses from the CPU, and the other is for all APICs to communicate.
const Addr PhysAddrAPICRangeSize = 1 << 12;
diff -r 7539092b28ac -r 55f9947891fb src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Sun Oct 12 13:54:57 2008 -0700
+++ b/src/cpu/BaseCPU.py Sun Oct 12 14:01:06 2008 -0700
@@ -97,7 +97,7 @@
dtb = Param.X86DTB(X86DTB(), "Data TLB")
itb = Param.X86ITB(X86ITB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
- _localApic = X86LocalApic(pio_addr=0xa000000000000000)
+ _localApic = X86LocalApic(pio_addr=0x2000000000000000)
interrupts = \
Param.X86LocalApic(_localApic, "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'mips':
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