changeset f4b9c344d1ca in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f4b9c344d1ca
description:
X86: Implement CPUID with a magical function instead of microcode.
diffstat:
6 files changed, 167 insertions(+), 202 deletions(-)
src/arch/x86/cpuid.cc | 80 +++
src/arch/x86/cpuid.hh | 30 +
src/arch/x86/isa/formats/cpuid.isa | 55 ++
src/arch/x86/isa/formats/formats.isa | 1
src/arch/x86/isa/insts/general_purpose/processor_information.py | 201
----------
src/arch/x86/isa/operands.isa | 2
diffs (truncated from 846 to 300 lines):
diff -r 55f9947891fb -r f4b9c344d1ca src/arch/x86/SConscript
--- a/src/arch/x86/SConscript Sun Oct 12 14:01:06 2008 -0700
+++ b/src/arch/x86/SConscript Sun Oct 12 15:31:28 2008 -0700
@@ -86,6 +86,7 @@
Import('*')
if env['TARGET_ISA'] == 'x86':
+ Source('cpuid.cc')
Source('emulenv.cc')
Source('floatregfile.cc')
Source('faults.cc')
@@ -173,7 +174,6 @@
'general_purpose/load_segment_registers.py',
'general_purpose/logical.py',
'general_purpose/no_operation.py',
- 'general_purpose/processor_information.py',
'general_purpose/rotate_and_shift/__init__.py',
'general_purpose/rotate_and_shift/rotate.py',
'general_purpose/rotate_and_shift/shift.py',
diff -r 55f9947891fb -r f4b9c344d1ca src/arch/x86/cpuid.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/x86/cpuid.cc Sun Oct 12 15:31:28 2008 -0700
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/cpuid.hh"
+#include "base/bitfield.hh"
+#include "cpu/thread_context.hh"
+
+namespace X86ISA {
+ enum StandardCpuidFunction {
+ VendorAndLargestStdFunc,
+ FamilyModelStepping,
+ NumStandardCpuidFuncs
+ };
+
+ enum ExtendedCpuidFunctions {
+ VendorAndLargestExtFunc,
+ FamilyModelSteppingBrandFeatures,
+ NameString1,
+ NameString2,
+ NameString3,
+ L1CacheAndTLB,
+ L2L3CacheAndL2TLB,
+ APMInfo,
+
+ /*
+ * The following are defined by the spec but not yet implemented
+ */
+/* LongModeAddressSize,
+ // Function 9 is reserved
+ SVMInfo = 10,
+ // Functions 11-24 are reserved
+ TLB1GBPageInfo = 25,
+ PerformanceInfo,*/
+
+ NumExtendedCpuidFuncs
+ };
+
+ static const int vendorStringSize = 13;
+ static const char vendorString[vendorStringSize] = "AuthenticAMD";
+ static const int nameStringSize = 48;
+ static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
+
+ uint64_t
+ stringToRegister(const char *str)
+ {
+ uint64_t reg = 0;
+ for (int pos = 3; pos >=0; pos--) {
+ reg <<= 8;
+ reg |= str[pos];
+ }
+ return reg;
+ }
+
+ bool
+ doCpuid(ThreadContext * tc, uint32_t function, CpuidResult &result)
+ {
+ uint16_t family = bits(function, 31, 16);
+ uint16_t funcNum = bits(function, 15, 0);
+ if (family == 0x8000) {
+ // The extended functions
+ switch (funcNum) {
+ case VendorAndLargestExtFunc:
+ assert(vendorStringSize >= 12);
+ result = CpuidResult(
+ NumExtendedCpuidFuncs - 1,
+ stringToRegister(vendorString),
+ stringToRegister(vendorString + 4),
+ stringToRegister(vendorString + 8));
+ break;
+ case FamilyModelSteppingBrandFeatures:
+ result = CpuidResult(0x00020f51, 0x00000405,
+ 0xe3d3fbff, 0x00000001);
+ break;
+ case NameString1:
+ case NameString2:
+ case NameString3:
+ {
+ // Zero fill anything beyond the end of the string. This
+ // should go away once the string is a vetted parameter.
+ char cleanName[nameStringSize];
+ memset(cleanName, '\0', nameStringSize);
+ strncpy(cleanName, nameString, nameStringSize);
+
+ int offset = (funcNum - NameString1) * 16;
+ assert(nameStringSize >= offset + 16);
+ result = CpuidResult(
+ stringToRegister(cleanName + offset + 0),
+ stringToRegister(cleanName + offset + 4),
+ stringToRegister(cleanName + offset + 8),
+ stringToRegister(cleanName + offset + 12));
+ }
+ break;
+ case L1CacheAndTLB:
+ result = CpuidResult(0xff08ff08, 0xff20ff20,
+ 0x40020140, 0x40020140);
+ break;
+ case L2L3CacheAndL2TLB:
+ result = CpuidResult(0x00000000, 0x42004200,
+ 0x00000000, 0x04008140);
+ break;
+ case APMInfo:
+ result = CpuidResult(0x80000018, 0x68747541,
+ 0x69746e65, 0x444d4163);
+ break;
+/* case LongModeAddressSize:
+ case SVMInfo:
+ case TLB1GBPageInfo:
+ case PerformanceInfo:*/
+ default:
+ return false;
+ }
+ } else if(family == 0x0000) {
+ // The standard functions
+ switch (funcNum) {
+ case VendorAndLargestStdFunc:
+ assert(vendorStringSize >= 12);
+ result = CpuidResult(
+ NumStandardCpuidFuncs - 1,
+ stringToRegister(vendorString),
+ stringToRegister(vendorString + 4),
+ stringToRegister(vendorString + 8));
+ break;
+ case FamilyModelStepping:
+ result = CpuidResult(0x00020f51, 0000000405,
+ 0xe3d3fbff, 0x00000001);
+ break;
+ default:
+ return false;
+ }
+ }
+ return true;
+ }
+} //namespace X86ISA
diff -r 55f9947891fb -r f4b9c344d1ca src/arch/x86/cpuid.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/x86/cpuid.hh Sun Oct 12 15:31:28 2008 -0700
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_CPUID_HH__
+#define __ARCH_X86_CPUID_HH__
+
+#include <inttypes.h>
+
+class ThreadContext;
+
+namespace X86ISA
+{
+ struct CpuidResult
+ {
+ uint64_t rax;
+ uint64_t rbx;
+ uint64_t rcx;
+ uint64_t rdx;
+
+ // These are not in alphebetical order on purpose. The order reflects
+ // how the CPUID orders the registers when it returns results.
+ CpuidResult(uint64_t _rax, uint64_t _rbx,
+ uint64_t _rdx, uint64_t _rcx) :
+ rax(_rax), rbx(_rbx), rcx(_rcx), rdx(_rdx)
+ {}
+
+ CpuidResult()
+ {}
+ };
+
+ bool doCpuid(ThreadContext * tc, uint32_t function, CpuidResult &result);
+} // namespace X86ISA
+
+#endif
diff -r 55f9947891fb -r f4b9c344d1ca
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun Oct 12 14:01:06
2008 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun Oct 12 15:31:28
2008 -0700
@@ -168,7 +168,7 @@
#if FULL_SYSTEM
0x05: syscall();
#else
- 0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall);
+ 0x05: SyscallInst::syscall('xc->syscall(Rax)', IsSyscall);
#endif
0x06: clts();
//sandpile.org says (AMD) after sysret, so I might want to
check
@@ -707,7 +707,14 @@
0x14: decode OPCODE_OP_BOTTOM3 {
0x0: push_fs();
0x1: pop_fs();
- 0x2: Inst::CPUID(rAd);
+ 0x2: CPUIDInst::CPUID({{
+ CpuidResult result;
+ success = doCpuid(xc->tcBase(), Rax, result);
+ Rax = result.rax;
+ Rbx = result.rbx;
+ Rcx = result.rcx;
+ Rdx = result.rdx;
+ }});
0x3: Inst::BT(Ev,Gv);
0x4: shld_Ev_Gv_Ib();
0x5: shld_Ev_Gv_rCl();
diff -r 55f9947891fb -r f4b9c344d1ca src/arch/x86/isa/formats/cpuid.isa
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/x86/isa/formats/cpuid.isa Sun Oct 12 15:31:28 2008 -0700
@@ -0,0 +1,110 @@
+// Copyright (c) 2008 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
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