changeset 443e6f925027 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=443e6f925027
description:
X86: Create a SeqOp class of microops and make Br one of them.
diffstat:
7 files changed, 109 insertions(+), 6 deletions(-)
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 2
src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
| 2
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
| 2
src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
| 2
src/arch/x86/isa/microops/microops.isa
| 1
src/arch/x86/isa/microops/regop.isa
| 2
src/arch/x86/isa/microops/seqop.isa
| 104 ++++++++++
diffs (truncated from 832 to 300 lines):
diff -r b7adf50863dc -r 443e6f925027
src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py
Sun Oct 12 15:31:37 2008 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py
Sun Oct 12 15:33:17 2008 -0700
@@ -246,7 +246,7 @@
divLoopTop:
div2 t1, rax, t1, dataSize=1
div2 t1, rax, t1, flags=(EZF,), dataSize=1
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax, dataSize=1
@@ -269,7 +269,7 @@
divLoopTop:
div2 t1, rax, t1, dataSize=1
div2 t1, rax, t1, flags=(EZF,), dataSize=1
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax, dataSize=1
@@ -293,7 +293,7 @@
divLoopTop:
div2 t1, rax, t1, dataSize=1
div2 t1, rax, t1, flags=(EZF,), dataSize=1
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax, dataSize=1
@@ -321,7 +321,7 @@
div2 t1, rax, t1
div2 t1, rax, t1
div2 t1, rax, t1, flags=(EZF,)
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax
@@ -347,7 +347,7 @@
div2 t1, rax, t1
div2 t1, rax, t1
div2 t1, rax, t1, flags=(EZF,)
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax
@@ -374,7 +374,7 @@
div2 t1, rax, t1
div2 t1, rax, t1
div2 t1, rax, t1, flags=(EZF,)
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax
@@ -422,7 +422,7 @@
divLoopTop:
div2 t4, t1, t4, dataSize=1
div2 t4, t1, t4, flags=(EZF,), dataSize=1
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5, dataSize=1
@@ -495,7 +495,7 @@
divLoopTop:
div2 t4, t1, t4, dataSize=1
div2 t4, t1, t4, flags=(EZF,), dataSize=1
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5, dataSize=1
@@ -569,7 +569,7 @@
divLoopTop:
div2 t4, t1, t4, dataSize=1
div2 t4, t1, t4, flags=(EZF,), dataSize=1
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5, dataSize=1
@@ -646,7 +646,7 @@
div2 t4, t1, t4
div2 t4, t1, t4
div2 t4, t1, t4, flags=(EZF,)
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5
@@ -721,7 +721,7 @@
div2 t4, t1, t4
div2 t4, t1, t4
div2 t4, t1, t4, flags=(EZF,)
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5
@@ -797,7 +797,7 @@
div2 t4, t1, t4
div2 t4, t1, t4
div2 t4, t1, t4, flags=(EZF,)
- bri t0, label("divLoopTop"), flags=(nCEZF,)
+ br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5
diff -r b7adf50863dc -r 443e6f925027
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
Sun Oct 12 15:31:37 2008 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
Sun Oct 12 15:33:17 2008 -0700
@@ -86,7 +86,7 @@
# Determine if the input was zero, and also move it to a temp reg.
movi t1, t1, t0, dataSize=8
and t1, regm, regm, flags=(ZF,)
- bri t0, label("end"), flags=(CZF,)
+ br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0x0
@@ -137,7 +137,7 @@
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
- bri t0, label("end"), flags=(CZF,)
+ br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0x0
@@ -189,7 +189,7 @@
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
- bri t0, label("end"), flags=(CZF,)
+ br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0x0
@@ -237,7 +237,7 @@
# Determine if the input was zero, and also move it to a temp reg.
mov t1, t1, t0, dataSize=8
and t1, regm, regm, flags=(ZF,)
- bri t0, label("end"), flags=(CZF,)
+ br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0
@@ -292,7 +292,7 @@
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
- bri t0, label("end"), flags=(CZF,)
+ br label("end"), flags=(CZF,)
# Zero out the result register
mov reg, reg, t0
@@ -348,7 +348,7 @@
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
- bri t0, label("end"), flags=(CZF,)
+ br label("end"), flags=(CZF,)
# Zero out the result register
mov reg, reg, t0
diff -r b7adf50863dc -r 443e6f925027
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Sun Oct 12 15:31:37 2008 -0700
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Sun Oct 12 15:33:17 2008 -0700
@@ -86,16 +86,16 @@
#temp_RFLAGS.VM != 1
rcri t0, t3, 18, flags=(ECF,)
- bri t0, label("protToVirtFallThrough"), flags=(nCECF,)
+ br label("protToVirtFallThrough"), flags=(nCECF,)
#CPL=0
rdm5reg t4
andi t0, t4, 0x30, flags=(EZF,)
- bri t0, label("protToVirtFallThrough"), flags=(nCEZF,)
+ br label("protToVirtFallThrough"), flags=(nCEZF,)
#(LEGACY_MODE)
rcri t0, t4, 1, flags=(ECF,)
- bri t0, label("protToVirtFallThrough"), flags=(nCECF,)
+ br label("protToVirtFallThrough"), flags=(nCECF,)
panic "iret to virtual mode not supported"
@@ -113,12 +113,12 @@
#CS = READ_DESCRIPTOR (temp_CS, iret_chk)
andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
- bri t0, label("processCSDescriptor"), flags=(CEZF,)
+ br label("processCSDescriptor"), flags=(CEZF,)
andi t6, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
- bri t0, label("globalCSDescriptor"), flags=(CEZF,)
+ br label("globalCSDescriptor"), flags=(CEZF,)
ld t6, tsl, [1, t0, t6], dataSize=8
- bri t0, label("processCSDescriptor")
+ br label("processCSDescriptor")
globalCSDescriptor:
ld t6, tsg, [1, t0, t6], dataSize=8
processCSDescriptor:
@@ -143,7 +143,7 @@
andi t0, t4, 0xE, flags=(EZF,)
# Since we just found out we're in 64 bit mode, take advantage and
# do the appropriate RIP checks.
- bri t0, label("doPopStackStuffAndCheckRIP"), flags=(CEZF,)
+ br label("doPopStackStuffAndCheckRIP"), flags=(CEZF,)
# Here, we know we're -not- in 64 bit mode, so we should do the
# appropriate/other RIP checks.
@@ -156,17 +156,17 @@
srli t7, t4, 4
xor t7, t7, t5
andi t0, t7, 0x3, flags=(EZF,)
- bri t0, label("doPopStackStuff"), flags=(nCEZF,)
+ br label("doPopStackStuff"), flags=(nCEZF,)
# We can modify user visible state here because we're know
# we're done with things that can fault.
addi rsp, rsp, "3 * env.stackSize"
- bri t0, label("fallThroughPopStackStuff")
+ br label("fallThroughPopStackStuff")
doPopStackStuffAndCheckRIP:
# Check if the RIP is canonical.
sra t7, t1, 47, flags=(EZF,), dataSize=ssz
# if t7 isn't 0 or -1, it wasn't canonical.
- bri t0, label("doPopStackStuff"), flags=(CEZF,)
+ br label("doPopStackStuff"), flags=(CEZF,)
addi t0, t7, 1, flags=(EZF,), dataSize=ssz
fault "new GeneralProtection(0)", flags=(nCEZF,)
@@ -177,12 +177,12 @@
ld t2, ss, [1, t0, rsp], "4 * env.dataSize", dataSize=ssz
# SS = READ_DESCRIPTOR (temp_SS, ss_chk)
andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
- bri t0, label("processSSDescriptor"), flags=(CEZF,)
+ br label("processSSDescriptor"), flags=(CEZF,)
andi t7, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
- bri t0, label("globalSSDescriptor"), flags=(CEZF,)
+ br label("globalSSDescriptor"), flags=(CEZF,)
ld t7, tsl, [1, t0, t7], dataSize=8
- bri t0, label("processSSDescriptor")
+ br label("processSSDescriptor")
globalSSDescriptor:
ld t7, tsg, [1, t0, t7], dataSize=8
processSSDescriptor:
@@ -208,7 +208,7 @@
srli t7, t4, 4
xor t7, t7, t5
andi t0, t7, 0x3, flags=(EZF,)
- bri t0, label("skipSegmentSquashing"), flags=(CEZF,)
+ br label("skipSegmentSquashing"), flags=(CEZF,)
# The attribute register needs to keep track of more info before this will
# work the way it needs to.
diff -r b7adf50863dc -r 443e6f925027
src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
Sun Oct 12 15:31:37 2008 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
Sun Oct 12 15:33:17 2008 -0700
@@ -97,12 +97,12 @@
# Do stuff if they're equal
andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
- bri t0, label("processDescriptor"), flags=(CEZF,)
+ br label("processDescriptor"), flags=(CEZF,)
andi t3, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
- bri t0, label("globalDescriptor"), flags=(CEZF,)
+ br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t3], dataSize=8
- bri t0, label("processDescriptor")
+ br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t3], dataSize=8
processDescriptor:
@@ -112,7 +112,7 @@
wrdl cs, t3, t2
wrsel cs, t2
wrip t0, t1
- bri t0, label("end")
+ br label("end")
# Do other stuff if they're not.
end:
diff -r b7adf50863dc -r 443e6f925027
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Sun Oct
12 15:31:37 2008 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Sun Oct
12 15:33:17 2008 -0700
@@ -240,12 +240,12 @@
def macroop MOV_S_R {
andi t0, regm, 0xFC, flags=(EZF,), dataSize=2
- bri t0, label("processDescriptor"), flags=(CEZF,)
+ br label("processDescriptor"), flags=(CEZF,)
andi t2, regm, 0xF8, dataSize=8
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