Kevin Lim wrote: > Hey Gabe, > > My suggestion would be to allow translation to be put off until it has > completed or generated a different fault. It would be a bit of a pain > to include, but given that the infrastructure is already there in > terms of delaying when cache misses occur, it should be feasible. I'll start working towards doing things this way with the simple CPU. There will be other things to change in o3 before this is an issue anyway, so if it doesn't scare you too badly I'm more comfortable putting us in that situation in the future.
> > Regarding the other downsides, assuming the TLBs are working properly, > then hopefully TLB misses shouldn't happen too often. For TLB hits, > ideally there should be a relatively fast response path that will > hopefully keep it from having too much overhead. What issues might > you foresee with ARM and this TLB configuration? ARM should work just like Alpha or MIPS or SPARC, but since I can't easily fix it up if there are any API changes it might end up being broken. I remember hearing this happened already, actually. I may be making that up. Gabe _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
