# HG changeset patch # User Korey Sewell <ksew...@umich.edu> # Date 1235138771 18000 # Node ID b6e4240c46e429bf99fefd0d61fef1465de86e49 # Parent 7a74edaa8741dd7fb541ef6d404dac3a9ebc86f9 imported patch inorder-alpha-port
diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/SConscript --- a/src/arch/SConscript Sun Feb 15 23:43:39 2009 -0800 +++ b/src/arch/SConscript Fri Feb 20 09:06:11 2009 -0500 @@ -51,6 +51,7 @@ isa_switch_hdrs = Split(''' locked_mem.hh microcode_rom.hh mmaped_ipr.hh + mt.hh process.hh predecoder.hh regfile.hh diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/floatregfile.hh --- a/src/arch/alpha/floatregfile.hh Sun Feb 15 23:43:39 2009 -0800 +++ b/src/arch/alpha/floatregfile.hh Fri Feb 20 09:06:11 2009 -0500 @@ -48,6 +48,13 @@ getFloatRegName(RegIndex) return ""; } +const int SingleWidth = 32; +const int SingleBytes = SingleWidth / 4; +const int DoubleWidth = 64; +const int DoubleBytes = DoubleWidth / 4; +const int QuadWidth = 128; +const int QuadBytes = QuadWidth / 4; + class FloatRegFile { public: @@ -60,6 +67,55 @@ class FloatRegFile void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + FloatReg + readReg(int floatReg) + { + return d[floatReg]; + } + + FloatReg + readReg(int floatReg, int width) + { + return readReg(floatReg); + } + + FloatRegBits + readRegBits(int floatReg) + { + return q[floatReg]; + } + + FloatRegBits + readRegBits(int floatReg, int width) + { + return readRegBits(floatReg); + } + + void + setReg(int floatReg, const FloatReg &val) + { + d[floatReg] = val; + } + + void + setReg(int floatReg, const FloatReg &val, int width) + { + setReg(floatReg, val); + } + + void + setRegBits(int floatReg, const FloatRegBits &val) + { + q[floatReg] = val; + } + + void + setRegBits(int floatReg, const FloatRegBits &val, int width) + { + setRegBits(floatReg, val); + } + }; } // namespace AlphaISA diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.cc --- a/src/arch/alpha/miscregfile.cc Sun Feb 15 23:43:39 2009 -0800 +++ b/src/arch/alpha/miscregfile.cc Fri Feb 20 09:06:11 2009 -0500 @@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp, UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); } +MiscRegFile::MiscRegFile(BaseCPU *_cpu) +{ + cpu = _cpu; + initializeIprTable(); +} + + MiscReg -MiscRegFile::readRegNoEffect(int misc_reg) +MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid ) { switch (misc_reg) { case MISCREG_FPCR: @@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re } MiscReg -MiscRegFile::readReg(int misc_reg, ThreadContext *tc) +MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid ) { switch (misc_reg) { case MISCREG_FPCR: @@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, Threa } void -MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val) +MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) { switch (misc_reg) { case MISCREG_FPCR: @@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg } void -MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc) +MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, + unsigned tid) { switch (misc_reg) { case MISCREG_FPCR: diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/miscregfile.hh --- a/src/arch/alpha/miscregfile.hh Sun Feb 15 23:43:39 2009 -0800 +++ b/src/arch/alpha/miscregfile.hh Fri Feb 20 09:06:11 2009 -0500 @@ -41,6 +41,7 @@ class Checkpoint; class ThreadContext; +class BaseCPU; namespace AlphaISA { @@ -74,6 +75,8 @@ class MiscRegFile InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + BaseCPU *cpu; + protected: InternalProcReg readIpr(int idx, ThreadContext *tc); void setIpr(int idx, InternalProcReg val, ThreadContext *tc); @@ -84,16 +87,18 @@ class MiscRegFile initializeIprTable(); } + MiscRegFile(BaseCPU *cpu); + // These functions should be removed once the simplescalar cpu // model has been replaced. int getInstAsid(); int getDataAsid(); - MiscReg readRegNoEffect(int misc_reg); - MiscReg readReg(int misc_reg, ThreadContext *tc); + MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0); + MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0); - void setRegNoEffect(int misc_reg, const MiscReg &val); - void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc); + void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0); + void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned tid = 0); void clear() @@ -107,6 +112,16 @@ class MiscRegFile void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + void reset(std::string core_name, unsigned num_threads, + unsigned num_vpes, BaseCPU *_cpu) + { } + + + void expandForMultithreading(unsigned num_threads, unsigned num_vpes) + { } + + }; void copyIprs(ThreadContext *src, ThreadContext *dest); diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/alpha/regfile.hh --- a/src/arch/alpha/regfile.hh Sun Feb 15 23:43:39 2009 -0800 +++ b/src/arch/alpha/regfile.hh Fri Feb 20 09:06:11 2009 -0500 @@ -32,6 +32,7 @@ #define __ARCH_ALPHA_REGFILE_HH__ #include "arch/alpha/isa_traits.hh" +#include "arch/alpha/mt.hh" #include "arch/alpha/floatregfile.hh" #include "arch/alpha/intregfile.hh" #include "arch/alpha/miscregfile.hh" diff -r 7a74edaa8741 -r b6e4240c46e4 src/arch/mips/regfile/misc_regfile.hh --- a/src/arch/mips/regfile/misc_regfile.hh Sun Feb 15 23:43:39 2009 -0800 +++ b/src/arch/mips/regfile/misc_regfile.hh Fri Feb 20 09:06:11 2009 -0500 @@ -69,7 +69,7 @@ namespace MipsISA public: MiscRegFile(); - MiscRegFile(BaseCPU *cpu); + MiscRegFile(BaseCPU *_cpu); void init(); diff -r 7a74edaa8741 -r b6e4240c46e4 src/cpu/inorder/cpu.cc --- a/src/cpu/inorder/cpu.cc Sun Feb 15 23:43:39 2009 -0800 +++ b/src/cpu/inorder/cpu.cc Fri Feb 20 09:06:11 2009 -0500 @@ -1284,13 +1284,13 @@ IntReg IntReg InOrderCPU::getSyscallArg(int idx, int tid) { - return readIntReg(ArgumentReg0 + idx, tid); + return readIntReg(ArgumentReg[0] + idx, tid); } void InOrderCPU::setSyscallArg(int idx, IntReg val, int tid) { - setIntReg(ArgumentReg0 + idx, val, tid); + setIntReg(ArgumentReg[0] + idx, val, tid); } void diff -r 7a74edaa8741 -r b6e4240c46e4 src/cpu/inorder/inorder_dyn_inst.hh --- a/src/cpu/inorder/inorder_dyn_inst.hh Sun Feb 15 23:43:39 2009 -0800 +++ b/src/cpu/inorder/inorder_dyn_inst.hh Fri Feb 20 09:06:11 2009 -0500 @@ -37,7 +37,9 @@ #include <list> #include <string> +#include "arch/isa_traits.hh" #include "arch/faults.hh" +#include "arch/types.hh" #include "base/fast_alloc.hh" #include "base/trace.hh" #include "cpu/inorder/inorder_trace.hh" @@ -47,11 +49,15 @@ #include "cpu/inst_seq.hh" #include "cpu/op_class.hh" #include "cpu/static_inst.hh" +//#include "cpu/inorder/cpu.hh" #include "cpu/inorder/thread_state.hh" #include "cpu/inorder/resource.hh" #include "cpu/inorder/pipeline_traits.hh" #include "mem/packet.hh" #include "sim/system.hh" + +using namespace TheISA; + /** * @file @@ -829,6 +835,10 @@ class InOrderDynInst : public FastAlloc, virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1); virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1); + /** Sets the number of consecutive store conditional failures. */ + void setStCondFailures(unsigned sc_failures) + { thread->storeCondFailures = sc_failures; } + ////////////////////////////////////////////////////////////// // // INSTRUCTION STATUS FLAGS (READ/SET) diff -r 7a74edaa8741 -r b6e4240c46e4 src/cpu/inorder/resources/cache_unit.cc --- a/src/cpu/inorder/resources/cache_unit.cc Sun Feb 15 23:43:39 2009 -0800 +++ b/src/cpu/inorder/resources/cache_unit.cc Fri Feb 20 09:06:11 2009 -0500 @@ -32,7 +32,7 @@ #include <vector> #include <list> #include "arch/isa_traits.hh" -#include "arch/mips/locked_mem.hh" +#include "arch/locked_mem.hh" #include "arch/utility.hh" #include "cpu/inorder/resources/cache_unit.hh" #include "cpu/inorder/pipeline_traits.hh" _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev