changeset bdef71accd68 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bdef71accd68
description:
CPU: Get rid of translate... functions from various interface classes.
diffstat:
19 files changed, 74 insertions(+), 420 deletions(-)
src/arch/x86/isa/microops/ldstop.isa | 13 ---
src/cpu/base_dyn_inst.hh | 56 ---------------
src/cpu/checker/cpu.cc | 55 ---------------
src/cpu/checker/cpu.hh | 4 -
src/cpu/checker/cpu_impl.hh | 2
src/cpu/inorder/cpu.hh | 18 ----
src/cpu/inorder/resources/tlb_unit.cc | 6 +
src/cpu/o3/cpu.hh | 18 ----
src/cpu/o3/fetch_impl.hh | 2
src/cpu/ozone/cpu.hh | 47 +-----------
src/cpu/ozone/front_end_impl.hh | 2
src/cpu/ozone/inorder_back_end.hh | 4 -
src/cpu/simple/atomic.cc | 117 --------------------------------
src/cpu/simple/atomic.hh | 5 -
src/cpu/simple/base.cc | 2
src/cpu/simple/timing.cc | 120 ++++++++++++++-------------------
src/cpu/simple/timing.hh | 6 -
src/cpu/simple_thread.hh | 15 ----
src/mem/request.hh | 2
diffs (truncated from 847 to 300 lines):
diff -r 02e5bc7ca9ba -r bdef71accd68 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Mon Feb 23 12:22:19 2009 -0800
+++ b/src/arch/x86/isa/microops/ldstop.isa Wed Feb 25 10:15:34 2009 -0800
@@ -454,7 +454,7 @@
Mem = Data;
Base = merge(Base, EA - SegBase, addressSize);
''');
-
+ defineMicroStoreOp('Cda', 'Mem = 0;', "Request::NO_ACCESS")
iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
{"code": "Data = merge(Data, EA, dataSize);",
@@ -493,17 +493,6 @@
microopClasses["tia"] = TiaOp
- iop = InstObjParams("cda", "Cda", 'X86ISA::LdStOp',
- {"code": '''
- Addr paddr;
- fault = xc->translateDataWriteAddr(EA, paddr,
- dataSize, (1 << segment));
- ''',
- "ea_code": calculateEA})
- header_output += MicroLeaDeclare.subst(iop)
- decoder_output += MicroLdStOpConstructor.subst(iop)
- exec_output += MicroLeaExecute.subst(iop)
-
class CdaOp(LdStOp):
def __init__(self, segment, addr, disp = 0,
dataSize="env.dataSize", addressSize="env.addressSize"):
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/base_dyn_inst.hh Wed Feb 25 10:15:34 2009 -0800
@@ -115,9 +115,6 @@
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
- Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags);
-
/**
* Does a write to a given address.
* @param data The data to be written.
@@ -130,9 +127,6 @@
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
- Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags);
-
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
Fault copySrcTranslate(Addr src);
@@ -857,29 +851,6 @@
};
template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags)
-{
- if (traceData) {
- traceData->setAddr(vaddr);
- }
-
- reqMade = true;
- Request *req = new Request();
- req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->contextId(), threadNumber);
-
- fault = cpu->translateDataReadReq(req, thread);
-
- if (fault == NoFault)
- paddr = req->getPaddr();
-
- delete req;
- return fault;
-}
-
-template<class Impl>
template<class T>
inline Fault
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
@@ -889,7 +860,7 @@
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->translateDataReadReq(req, thread);
+ fault = cpu->dtb->translate(req, thread->getTC(), false);
if (req->isUncacheable())
isUncacheable = true;
@@ -931,29 +902,6 @@
}
template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags)
-{
- if (traceData) {
- traceData->setAddr(vaddr);
- }
-
- reqMade = true;
- Request *req = new Request();
- req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->contextId(), threadNumber);
-
- fault = cpu->translateDataWriteReq(req, thread);
-
- if (fault == NoFault)
- paddr = req->getPaddr();
-
- delete req;
- return fault;
-}
-
-template<class Impl>
template<class T>
inline Fault
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
@@ -968,7 +916,7 @@
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->translateDataWriteReq(req, thread);
+ fault = cpu->dtb->translate(req, thread->getTC(), true);
if (req->isUncacheable())
isUncacheable = true;
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/checker/cpu.cc Wed Feb 25 10:15:34 2009 -0800
@@ -159,7 +159,7 @@
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- translateDataReadReq(memReq);
+ dtb->translate(memReq, tc, false);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
@@ -229,7 +229,7 @@
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- thread->translateDataWriteReq(memReq);
+ dtb->translate(memReq, tc, true);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that
@@ -325,57 +325,6 @@
#endif // FULL_SYSTEM
bool
-CheckerCPU::translateInstReq(Request *req)
-{
-#if FULL_SYSTEM
- return (thread->translateInstReq(req) == NoFault);
-#else
- thread->translateInstReq(req);
- return true;
-#endif
-}
-
-void
-CheckerCPU::translateDataReadReq(Request *req)
-{
- thread->translateDataReadReq(req);
-
- if (req->getVaddr() != unverifiedReq->getVaddr()) {
- warn("%lli: Request virtual addresses do not match! Inst: %#x, "
- "checker: %#x",
- curTick, unverifiedReq->getVaddr(), req->getVaddr());
- handleError();
- }
- req->setPaddr(unverifiedReq->getPaddr());
-
- if (checkFlags(req)) {
- warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
- curTick, unverifiedReq->getFlags(), req->getFlags());
- handleError();
- }
-}
-
-void
-CheckerCPU::translateDataWriteReq(Request *req)
-{
- thread->translateDataWriteReq(req);
-
- if (req->getVaddr() != unverifiedReq->getVaddr()) {
- warn("%lli: Request virtual addresses do not match! Inst: %#x, "
- "checker: %#x",
- curTick, unverifiedReq->getVaddr(), req->getVaddr());
- handleError();
- }
- req->setPaddr(unverifiedReq->getPaddr());
-
- if (checkFlags(req)) {
- warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
- curTick, unverifiedReq->getFlags(), req->getFlags());
- handleError();
- }
-}
-
-bool
CheckerCPU::checkFlags(Request *req)
{
// Remove any dynamic flags that don't have to do with the request itself.
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/checker/cpu.hh Wed Feb 25 10:15:34 2009 -0800
@@ -331,10 +331,6 @@
this->dtb->demapPage(vaddr, asn);
}
- bool translateInstReq(Request *req);
- void translateDataWriteReq(Request *req);
- void translateDataReadReq(Request *req);
-
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/checker/cpu_impl.hh Wed Feb 25 10:15:34 2009 -0800
@@ -155,7 +155,7 @@
fetch_PC, thread->contextId(),
inst->threadNumber);
- bool succeeded = translateInstReq(memReq);
+ bool succeeded = itb->translate(memReq, thread);
if (!succeeded) {
if (inst->getFault() == NoFault) {
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/inorder/cpu.hh Wed Feb 25 10:15:34 2009 -0800
@@ -498,24 +498,6 @@
/** Debug function to print all instructions on the list. */
void dumpInsts();
- /** Translates instruction requestion in syscall emulation mode. */
- Fault translateInstReq(RequestPtr &req, Thread *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-
- /** Translates data read request in syscall emulation mode. */
- Fault translateDataReadReq(RequestPtr &req, Thread *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-
- /** Translates data write request in syscall emulation mode. */
- Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
- {
- return thread->getProcessPtr()->pTable->translate(req);
- }
-
/** Forwards an instruction read to the appropriate data
* resource (indexes into Resource Pool thru "dataPortIdx")
*/
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/inorder/resources/tlb_unit.cc Wed Feb 25 10:15:34 2009 -0800
@@ -98,7 +98,8 @@
case FetchLookup:
{
tlb_req->fault =
- this->cpu->translateInstReq(tlb_req->memReq, cpu->thread[tid]);
+ this->cpu->itb->translate(tlb_req->memReq,
+ cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
DPRINTF(Resource, "[tid:%i]: %s encountered while translating "
@@ -128,7 +129,8 @@
tid, seq_num, tlb_req->memReq->getVaddr());
tlb_req->fault =
- this->cpu->translateInstReq(tlb_req->memReq, cpu->thread[tid]);
+ this->cpu->itb->translate(tlb_req->memReq,
+ cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
DPRINTF(Resource, "[tid:%i]: %s encountered while translating "
diff -r 02e5bc7ca9ba -r bdef71accd68 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Mon Feb 23 12:22:19 2009 -0800
+++ b/src/cpu/o3/cpu.hh Wed Feb 25 10:15:34 2009 -0800
@@ -279,24 +279,6 @@
this->dtb->demapPage(vaddr, asn);
}
- /** Translates instruction requestion. */
- Fault translateInstReq(RequestPtr &req, Thread *thread)
- {
- return this->itb->translate(req, thread->getTC());
- }
-
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