changeset 73084c6bb183 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=73084c6bb183
description:
ISA: Replace the translate functions in the TLBs with translateAtomic.
diffstat:
21 files changed, 40 insertions(+), 38 deletions(-)
src/arch/alpha/tlb.cc | 4 ++--
src/arch/alpha/tlb.hh | 4 ++--
src/arch/mips/tlb.cc | 4 ++--
src/arch/mips/tlb.hh | 5 +++--
src/arch/sparc/tlb.cc | 4 ++--
src/arch/sparc/tlb.hh | 4 ++--
src/arch/x86/tlb.cc | 11 ++++++-----
src/arch/x86/tlb.hh | 6 +++---
src/cpu/base_dyn_inst.hh | 4 ++--
src/cpu/checker/cpu.cc | 4 ++--
src/cpu/checker/cpu_impl.hh | 2 +-
src/cpu/inorder/resources/tlb_unit.cc | 4 ++--
src/cpu/o3/fetch_impl.hh | 2 +-
src/cpu/ozone/front_end_impl.hh | 2 +-
src/cpu/ozone/inorder_back_end.hh | 4 ++--
src/cpu/simple/atomic.cc | 4 ++--
src/cpu/simple/base.cc | 2 +-
src/cpu/simple/timing.cc | 2 +-
src/cpu/simple_thread.hh | 2 +-
src/sim/tlb.cc | 2 +-
src/sim/tlb.hh | 2 +-
diffs (truncated from 391 to 300 lines):
diff -r bdef71accd68 -r 73084c6bb183 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/alpha/tlb.cc Wed Feb 25 10:15:44 2009 -0800
@@ -317,7 +317,7 @@
}
Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM && PcPAL(req->getPC()))
@@ -479,7 +479,7 @@
}
Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
Addr pc = tc->readPC();
diff -r bdef71accd68 -r 73084c6bb183 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/alpha/tlb.hh Wed Feb 25 10:15:44 2009 -0800
@@ -131,7 +131,7 @@
ITB(const Params *p);
virtual void regStats();
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB
@@ -155,7 +155,7 @@
DTB(const Params *p);
virtual void regStats();
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
};
} // namespace AlphaISA
diff -r bdef71accd68 -r 73084c6bb183 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/mips/tlb.cc Wed Feb 25 10:15:44 2009 -0800
@@ -310,7 +310,7 @@
}
Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();
@@ -427,7 +427,7 @@
}
Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();
diff -r bdef71accd68 -r 73084c6bb183 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/mips/tlb.hh Wed Feb 25 10:15:44 2009 -0800
@@ -145,7 +145,7 @@
typedef MipsTLBParams Params;
ITB(const Params *p);
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
};
class DTB : public TLB {
@@ -153,7 +153,8 @@
typedef MipsTLBParams Params;
DTB(const Params *p);
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+ bool write = false);
};
class UTB : public ITB, public DTB {
diff -r bdef71accd68 -r 73084c6bb183 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/sparc/tlb.cc Wed Feb 25 10:15:44 2009 -0800
@@ -436,7 +436,7 @@
}
Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
@@ -549,7 +549,7 @@
}
Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
/*
* @todo this could really use some profiling and fixing to make
diff -r bdef71accd68 -r 73084c6bb183 src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/sparc/tlb.hh Wed Feb 25 10:15:44 2009 -0800
@@ -177,7 +177,7 @@
cacheEntry = NULL;
}
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
private:
void writeSfsr(bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
@@ -199,7 +199,7 @@
cacheEntry[1] = NULL;
}
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff -r bdef71accd68 -r 73084c6bb183 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/x86/tlb.cc Wed Feb 25 10:15:44 2009 -0800
@@ -190,7 +190,8 @@
template<class TlbFault>
Fault
-TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
+TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
+ bool write, bool execute)
{
Addr vaddr = req->getVaddr();
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
@@ -662,15 +663,15 @@
};
Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
{
- return TLB::translate<FakeDTLBFault>(req, tc, write, false);
+ return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
}
Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
{
- return TLB::translate<FakeITLBFault>(req, tc, false, true);
+ return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
}
#if FULL_SYSTEM
diff -r bdef71accd68 -r 73084c6bb183 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/arch/x86/tlb.hh Wed Feb 25 10:15:44 2009 -0800
@@ -138,7 +138,7 @@
EntryList entryList;
template<class TlbFault>
- Fault translate(RequestPtr &req, ThreadContext *tc,
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
bool write, bool execute);
public:
@@ -159,7 +159,7 @@
_allowNX = false;
}
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
friend class DTB;
};
@@ -172,7 +172,7 @@
{
_allowNX = true;
}
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/base_dyn_inst.hh Wed Feb 25 10:15:44 2009 -0800
@@ -860,7 +860,7 @@
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->dtb->translate(req, thread->getTC(), false);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), false);
if (req->isUncacheable())
isUncacheable = true;
@@ -916,7 +916,7 @@
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->dtb->translate(req, thread->getTC(), true);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), true);
if (req->isUncacheable())
isUncacheable = true;
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/checker/cpu.cc Wed Feb 25 10:15:44 2009 -0800
@@ -159,7 +159,7 @@
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- dtb->translate(memReq, tc, false);
+ dtb->translateAtomic(memReq, tc, false);
PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
@@ -229,7 +229,7 @@
memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
- dtb->translate(memReq, tc, true);
+ dtb->translateAtomic(memReq, tc, true);
// Can compare the write data and result only if it's cacheable,
// not a store conditional, or is a store conditional that
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/checker/cpu_impl.hh Wed Feb 25 10:15:44 2009 -0800
@@ -155,7 +155,7 @@
fetch_PC, thread->contextId(),
inst->threadNumber);
- bool succeeded = itb->translate(memReq, thread);
+ bool succeeded = itb->translateAtomic(memReq, thread);
if (!succeeded) {
if (inst->getFault() == NoFault) {
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/inorder/resources/tlb_unit.cc Wed Feb 25 10:15:44 2009 -0800
@@ -98,7 +98,7 @@
case FetchLookup:
{
tlb_req->fault =
- this->cpu->itb->translate(tlb_req->memReq,
+ this->cpu->itb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
@@ -129,7 +129,7 @@
tid, seq_num, tlb_req->memReq->getVaddr());
tlb_req->fault =
- this->cpu->itb->translate(tlb_req->memReq,
+ this->cpu->itb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/o3/fetch_impl.hh Wed Feb 25 10:15:44 2009 -0800
@@ -599,7 +599,7 @@
memReq[tid] = mem_req;
// Translate the instruction request.
- fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC());
+ fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
// In the case of faults, the fetch stage may need to stall and wait
// for the ITB miss to be handled.
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/ozone/front_end_impl.hh
--- a/src/cpu/ozone/front_end_impl.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/ozone/front_end_impl.hh Wed Feb 25 10:15:44 2009 -0800
@@ -480,7 +480,7 @@
PC, cpu->thread->contextId());
// Translate the instruction request.
- fault = cpu->itb->translate(memReq, thread);
+ fault = cpu->itb->translateAtomic(memReq, thread);
// Now do the timing access to see whether or not the instruction
// exists within the cache.
diff -r bdef71accd68 -r 73084c6bb183 src/cpu/ozone/inorder_back_end.hh
--- a/src/cpu/ozone/inorder_back_end.hh Wed Feb 25 10:15:34 2009 -0800
+++ b/src/cpu/ozone/inorder_back_end.hh Wed Feb 25 10:15:44 2009 -0800
@@ -204,7 +204,7 @@
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
- Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false);
+ Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
// if we have a cache, do cache access too
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