changeset 41b18fe25a0e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=41b18fe25a0e
description:
SPARC: Adjust a few instructions to not write registers in initiateAcc.
diffstat:
3 files changed, 27 insertions(+), 15 deletions(-)
src/arch/sparc/isa/decoder.isa | 18 ++++++++----------
src/arch/sparc/isa/formats/mem/basicmem.isa | 10 ++++++++++
src/arch/sparc/isa/formats/mem/util.isa | 14 +++++++++-----
diffs (79 lines):
diff -r a0ef4a6349dc -r 41b18fe25a0e src/arch/sparc/isa/decoder.isa
--- a/src/arch/sparc/isa/decoder.isa Wed Feb 25 10:15:56 2009 -0800
+++ b/src/arch/sparc/isa/decoder.isa Wed Feb 25 10:16:04 2009 -0800
@@ -1231,16 +1231,14 @@
0x23: Load::lddf({{Frd.udw = Mem.udw;}});
0x24: Store::stf({{Mem.uw = Frds.uw;}});
0x25: decode RD {
- 0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
- if (fault)
- return fault;
- Mem.uw = Fsr<31:0>;
- Fsr = insertBits(Fsr,16,14,0);}});
- 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
- if (fault)
- return fault;
- Mem.udw = Fsr;
- Fsr = insertBits(Fsr,16,14,0);}});
+ 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
+ if (fault)
+ return fault;
+ Mem.uw = Fsr<31:0>;}});
+ 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
+ if (fault)
+ return fault;
+ Mem.udw = Fsr;}});
default: FailUnimpl::stfsrOther();
}
0x26: stqf({{fault = new FpDisabled;}});
diff -r a0ef4a6349dc -r 41b18fe25a0e src/arch/sparc/isa/formats/mem/basicmem.isa
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa Wed Feb 25 10:15:56
2009 -0800
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa Wed Feb 25 10:16:04
2009 -0800
@@ -108,6 +108,16 @@
StoreFuncs, '', name, Name, 0, opt_flags)
}};
+def format StoreFsr(code, *opt_flags) {{
+ code = filterDoubles(code)
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doMemFormat(code,
+ StoreFuncs, '', name, Name, 0, opt_flags,
+ 'Fsr = insertBits(Fsr,16,14,0);')
+}};
+
def format TwinLoad(code, *opt_flags) {{
(header_output,
decoder_output,
diff -r a0ef4a6349dc -r 41b18fe25a0e src/arch/sparc/isa/formats/mem/util.isa
--- a/src/arch/sparc/isa/formats/mem/util.isa Wed Feb 25 10:15:56 2009 -0800
+++ b/src/arch/sparc/isa/formats/mem/util.isa Wed Feb 25 10:16:04 2009 -0800
@@ -264,11 +264,6 @@
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
- if(fault == NoFault)
- {
- //Write the resulting state to the execution context
- %(op_wb)s;
- }
return fault;
}
}};
@@ -277,6 +272,15 @@
Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
Trace::InstRecord * traceData) const
{
+ Fault fault = NoFault;
+ %(op_decl)s;
+
+ %(op_rd)s;
+ %(postacc_code)s;
+ if (fault == NoFault)
+ {
+ %(op_wb)s;
+ }
return NoFault;
}
}};
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