changeset 8091ac99341a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8091ac99341a
description:
CPU: Implement translateTiming which defers to translateAtomic, and
convert the timing simple CPU to use it.
diffstat:
15 files changed, 454 insertions(+), 198 deletions(-)
src/arch/alpha/tlb.cc | 20 ++
src/arch/alpha/tlb.hh | 8
src/arch/mips/tlb.cc | 20 ++
src/arch/mips/tlb.hh | 8
src/arch/sparc/tlb.cc | 20 ++
src/arch/sparc/tlb.hh | 9 -
src/arch/x86/tlb.cc | 22 ++
src/arch/x86/tlb.hh | 12 +
src/cpu/simple/atomic.cc | 6
src/cpu/simple/base.cc | 6
src/cpu/simple/base.hh | 4
src/cpu/simple/timing.cc | 378 +++++++++++++++++++++++++---------------------
src/cpu/simple/timing.hh | 114 +++++++++++++
src/sim/tlb.cc | 8
src/sim/tlb.hh | 17 ++
diffs (truncated from 1012 to 300 lines):
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/alpha/tlb.cc Wed Feb 25 10:16:15 2009 -0800
@@ -317,7 +317,7 @@
}
Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM && PcPAL(req->getPC()))
@@ -401,6 +401,14 @@
}
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
///////////////////////////////////////////////////////////////////////
//
// Alpha DTB
@@ -479,7 +487,7 @@
}
Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
Addr pc = tc->readPC();
@@ -616,6 +624,14 @@
return checkCacheability(req);
}
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
TlbEntry &
TLB::index(bool advance)
{
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/alpha/tlb.hh Wed Feb 25 10:16:15 2009 -0800
@@ -131,7 +131,9 @@
ITB(const Params *p);
virtual void regStats();
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation);
};
class DTB : public TLB
@@ -155,7 +157,9 @@
DTB(const Params *p);
virtual void regStats();
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write);
};
} // namespace AlphaISA
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/mips/tlb.cc Wed Feb 25 10:16:15 2009 -0800
@@ -310,7 +310,7 @@
}
Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();
@@ -426,8 +426,16 @@
#endif
}
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();
@@ -564,6 +572,14 @@
#endif
}
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
///////////////////////////////////////////////////////////////////////
//
// Mips ITB
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/mips/tlb.hh Wed Feb 25 10:16:15 2009 -0800
@@ -145,7 +145,9 @@
typedef MipsTLBParams Params;
ITB(const Params *p);
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation);
};
class DTB : public TLB {
@@ -153,8 +155,10 @@
typedef MipsTLBParams Params;
DTB(const Params *p);
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc,
bool write = false);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write = false);
};
class UTB : public ITB, public DTB {
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/sparc/tlb.cc Wed Feb 25 10:16:15 2009 -0800
@@ -436,7 +436,7 @@
}
Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
@@ -548,8 +548,16 @@
return NoFault;
}
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
/*
* @todo this could really use some profiling and fixing to make
@@ -847,6 +855,14 @@
return NoFault;
};
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
#if FULL_SYSTEM
Tick
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/sparc/tlb.hh Wed Feb 25 10:16:15 2009 -0800
@@ -177,7 +177,9 @@
cacheEntry = NULL;
}
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation);
private:
void writeSfsr(bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
@@ -199,7 +201,10 @@
cacheEntry[1] = NULL;
}
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr req,
+ ThreadContext *tc, bool write=false);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write=false);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/x86/tlb.cc Wed Feb 25 10:16:15 2009 -0800
@@ -190,7 +190,7 @@
template<class TlbFault>
Fault
-TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
bool write, bool execute)
{
Addr vaddr = req->getVaddr();
@@ -663,17 +663,33 @@
};
Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
{
return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
}
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
{
return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
}
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation)
+{
+ assert(translation);
+ translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
#if FULL_SYSTEM
Tick
diff -r 41b18fe25a0e -r 8091ac99341a src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Wed Feb 25 10:16:04 2009 -0800
+++ b/src/arch/x86/tlb.hh Wed Feb 25 10:16:15 2009 -0800
@@ -138,8 +138,10 @@
EntryList entryList;
template<class TlbFault>
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc,
bool write, bool execute);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write, bool execute);
public:
@@ -159,7 +161,9 @@
_allowNX = false;
}
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation);
friend class DTB;
};
@@ -172,7 +176,9 @@
{
_allowNX = true;
}
- Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, bool write);
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