changeset 7a323daa3df2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7a323daa3df2
description:
X86: Implement the LTR instruction.
diffstat:
2 files changed, 49 insertions(+), 1 deletion(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 -
src/arch/x86/isa/insts/system/segmentation.py | 48 +++++++++++++++++++++++++
diffs (70 lines):
diff -r 76fc2c3e10d2 -r 7a323daa3df2
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:17:08
2009 -0800
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:17:14
2009 -0800
@@ -94,7 +94,7 @@
0x0: sldt_Mw_or_Rv();
0x1: str_Mw_or_Rv();
0x2: lldt_Mw_or_Rv();
- 0x3: ltr_Mw_or_Rv();
+ 0x3: Inst::LTR(Ew);
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
//0x6: jmpe_Ev(); // IA-64
diff -r 76fc2c3e10d2 -r 7a323daa3df2
src/arch/x86/isa/insts/system/segmentation.py
--- a/src/arch/x86/isa/insts/system/segmentation.py Wed Feb 25 10:17:08
2009 -0800
+++ b/src/arch/x86/isa/insts/system/segmentation.py Wed Feb 25 10:17:14
2009 -0800
@@ -168,6 +168,54 @@
wrlimit idtr, t1
};
+def macroop LTR_R
+{
+ chks reg, t0, TRCheck
+ limm t4, 0
+ srli t4, reg, 3, dataSize=2
+ ldst t1, tsg, [8, t4, t0], dataSize=8
+ ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ chks reg, t1, TSSCheck
+ wrdh t3, t1, t2
+ wrdl tr, t1, reg
+ wrbase tr, t3, dataSize=8
+ ori t1, t1, (1 << 9)
+ st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_M
+{
+ ld t5, seg, sib, disp, dataSize=2
+ chks t5, t0, TRCheck
+ limm t4, 0
+ srli t4, t5, 3, dataSize=2
+ ldst t1, tsg, [8, t4, t0], dataSize=8
+ ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ chks t5, t1, TSSCheck
+ wrdh t3, t1, t2
+ wrdl tr, t1, t5
+ wrbase tr, t3, dataSize=8
+ ori t1, t1, (1 << 9)
+ st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_P
+{
+ rdip t7
+ ld t5, seg, riprel, disp, dataSize=2
+ chks t5, t0, TRCheck
+ limm t4, 0
+ srli t4, t5, 3, dataSize=2
+ ldst t1, tsg, [8, t4, t0], dataSize=8
+ ld t2, tsg, [8, t4, t0], 8, dataSize=8
+ chks t5, t1, TSSCheck
+ wrdh t3, t1, t2
+ wrdl tr, t1, t5
+ wrbase tr, t3, dataSize=8
+ ori t1, t1, (1 << 9)
+ st t1, tsg, [8, t4, t0], dataSize=8
+};
+
def macroop SWAPGS
{
rdval t1, kernel_gs_base, dataSize=8
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