changeset c92d57f579b1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c92d57f579b1
description:
CPU: Don't fetch when executing a macroop.
If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
diffstat:
2 files changed, 3 insertions(+), 3 deletions(-)
src/cpu/simple/atomic.cc | 4 ++--
src/cpu/simple/timing.cc | 2 +-
diffs (33 lines):
diff -r f2bfe08dc873 -r c92d57f579b1 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Wed Feb 25 10:18:29 2009 -0800
+++ b/src/cpu/simple/atomic.cc Wed Feb 25 10:18:36 2009 -0800
@@ -607,7 +607,7 @@
Fault fault = NoFault;
bool fromRom = isRomMicroPC(thread->readMicroPC());
- if (!fromRom) {
+ if (!fromRom && !curMacroStaticInst) {
setupFetchRequest(&ifetch_req);
fault = thread->itb->translateAtomic(&ifetch_req, tc);
}
@@ -617,7 +617,7 @@
bool icache_access = false;
dcache_access = false; // assume no dcache access
- if (!fromRom) {
+ if (!fromRom && !curMacroStaticInst) {
// This is commented out because the predecoder would act like
// a tiny cache otherwise. It wouldn't be flushed when needed
// like the I cache. It should be flushed, and when that works
diff -r f2bfe08dc873 -r c92d57f579b1 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Wed Feb 25 10:18:29 2009 -0800
+++ b/src/cpu/simple/timing.cc Wed Feb 25 10:18:36 2009 -0800
@@ -667,7 +667,7 @@
bool fromRom = isRomMicroPC(thread->readMicroPC());
- if (!fromRom) {
+ if (!fromRom && !curMacroStaticInst) {
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);
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