changeset 156cc0770e74 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=156cc0770e74
description:
CPU: Update stats now that there's no fetch in the middle of macroops.
diffstat:
21 files changed, 273 insertions(+), 270 deletions(-)
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout | 10 -
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt | 38 +++----
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout | 1
tests/long/00.gzip/ref/x86/linux/simple-timing/simout | 8 -
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt | 50 ++++-----
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout | 10 -
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 38 +++----
tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 8 -
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt | 50 ++++-----
tests/long/20.parser/ref/x86/linux/simple-timing/simout | 8 -
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt | 52 +++++-----
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout | 10 -
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt | 52 +++++-----
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout | 8 -
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt | 40 +++----
tests/long/70.twolf/ref/sparc/linux/simple-timing/simout | 12 +-
tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt | 36 +++---
tests/long/70.twolf/ref/x86/linux/simple-timing/simout | 8 -
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | 48 ++++-----
tests/quick/00.hello/ref/x86/linux/simple-timing/simout | 8 -
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt | 48 ++++-----
diffs (truncated from 1348 to 300 lines):
diff -r c92d57f579b1 -r 156cc0770e74
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout Wed Feb 25
10:18:36 2009 -0800
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout Wed Feb 25
10:18:45 2009 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:50:17
-M5 executing on zizzer
+M5 compiled Feb 24 2009 01:30:29
+M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
+M5 started Feb 24 2009 01:30:33
+M5 executing on tater
command line: build/SPARC_SE/m5.fast -d
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re
tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -43,4 +43,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2080416155000 because target called exit()
+Exiting @ tick 2076000961000 because target called exit()
diff -r c92d57f579b1 -r 156cc0770e74
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt Wed Feb
25 10:18:36 2009 -0800
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt Wed Feb
25 10:18:45 2009 -0800
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1502574 #
Simulator instruction rate (inst/s)
-host_mem_usage 205236 #
Number of bytes of host memory used
-host_seconds 991.31 #
Real time elapsed on the host
-host_tick_rate 2098643273 #
Simulator tick rate (ticks/s)
+host_inst_rate 779483 #
Simulator instruction rate (inst/s)
+host_mem_usage 204800 #
Number of bytes of host memory used
+host_seconds 1910.91 #
Real time elapsed on the host
+host_tick_rate 1086392421 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1489523295 #
Number of instructions simulated
-sim_seconds 2.080416 #
Number of seconds simulated
-sim_ticks 2080416155000 #
Number of ticks simulated
+sim_seconds 2.076001 #
Number of seconds simulated
+sim_ticks 2076000961000 #
Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402512844 #
number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994
# average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994
# average ReadReq mshr miss latency
@@ -77,14 +77,14 @@
system.cpu.dcache.replacements 449125 #
number of replacements
system.cpu.dcache.sampled_refs 453221 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.205833 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.229973 #
Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 596368000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 567696000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316420 #
number of writebacks
-system.cpu.icache.ReadReq_accesses 1489528206 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 1485113012 #
number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482
# average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1489527099 #
number of ReadReq hits
+system.cpu.icache.ReadReq_hits 1485111905 #
number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 61824000 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1107 #
number of ReadReq misses
@@ -93,16 +93,16 @@
system.cpu.icache.ReadReq_mshr_misses 1107 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1345552.934959
# Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1341564.503162
# Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 1489528206 #
number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 1485113012 #
number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55848.238482 #
average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482
# average overall mshr miss latency
-system.cpu.icache.demand_hits 1489527099 #
number of demand (read+write) hits
+system.cpu.icache.demand_hits 1485111905 #
number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 61824000 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 #
miss rate for demand accesses
system.cpu.icache.demand_misses 1107 #
number of demand (read+write) misses
@@ -113,11 +113,11 @@
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1489528206 #
number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 1485113012 #
number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482
# average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1489527099 #
number of overall hits
+system.cpu.icache.overall_hits 1485111905 #
number of overall hits
system.cpu.icache.overall_miss_latency 61824000 #
number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 #
miss rate for overall accesses
system.cpu.icache.overall_misses 1107 #
number of overall misses
@@ -130,8 +130,8 @@
system.cpu.icache.replacements 118 #
number of replacements
system.cpu.icache.sampled_refs 1107 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 906.330613 #
Cycle average of tags in use
-system.cpu.icache.total_refs 1489527099 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 906.413769 #
Cycle average of tags in use
+system.cpu.icache.total_refs 1485111905 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
system.cpu.idle_fraction 0 #
Percentage of idle cycles
@@ -204,12 +204,12 @@
system.cpu.l2cache.replacements 82905 #
number of replacements
system.cpu.l2cache.sampled_refs 98339 #
Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0
# number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16356.207611 #
Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 16358.028924 #
Cycle average of tags in use
system.cpu.l2cache.total_refs 337181 #
Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61861 #
number of writebacks
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
-system.cpu.numCycles 4160832310 #
number of cpu cycles simulated
+system.cpu.numCycles 4152001922 #
number of cpu cycles simulated
system.cpu.num_insts 1489523295 #
Number of instructions executed
system.cpu.num_refs 569365767 #
Number of memory references
system.cpu.workload.PROG:num_syscalls 49 #
Number of system calls
diff -r c92d57f579b1 -r 156cc0770e74
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout Wed Feb 25
10:18:36 2009 -0800
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout Wed Feb 25
10:18:45 2009 -0800
@@ -26,6 +26,7 @@
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
+info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
diff -r c92d57f579b1 -r 156cc0770e74
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout Wed Feb 25
10:18:36 2009 -0800
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout Wed Feb 25
10:18:45 2009 -0800
@@ -5,9 +5,9 @@
All Rights Reserved
-M5 compiled Feb 23 2009 23:45:19
-M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
-M5 started Feb 23 2009 23:48:10
+M5 compiled Feb 24 2009 01:30:29
+M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
+M5 started Feb 24 2009 01:41:46
M5 executing on tater
command line: build/X86_SE/m5.fast -d
build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py
long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -44,4 +44,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2554084828000 because target called exit()
+Exiting @ tick 1814744167000 because target called exit()
diff -r c92d57f579b1 -r 156cc0770e74
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt Wed Feb 25
10:18:36 2009 -0800
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt Wed Feb 25
10:18:45 2009 -0800
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 751612 #
Simulator instruction rate (inst/s)
-host_mem_usage 204588 #
Number of bytes of host memory used
-host_seconds 2154.53 #
Real time elapsed on the host
-host_tick_rate 1185451424 #
Simulator tick rate (ticks/s)
+host_inst_rate 759916 #
Simulator instruction rate (inst/s)
+host_mem_usage 204700 #
Number of bytes of host memory used
+host_seconds 2130.98 #
Real time elapsed on the host
+host_tick_rate 851601124 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1619365942 #
Number of instructions simulated
-sim_seconds 2.554085 #
Number of seconds simulated
-sim_ticks 2554084828000 #
Number of ticks simulated
+sim_seconds 1.814744 #
Number of seconds simulated
+sim_ticks 1814744167000 #
Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 418962758 #
number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697
# average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697
# average ReadReq mshr miss latency
@@ -67,61 +67,61 @@
system.cpu.dcache.replacements 439707 #
number of replacements
system.cpu.dcache.sampled_refs 443803 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.610676 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4094.900260 #
Cycle average of tags in use
system.cpu.dcache.total_refs 606705011 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1592465000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 779366000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 308507 #
number of writebacks
-system.cpu.icache.ReadReq_accesses 1925857355 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 1186516694 #
number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000
# average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1925856634 #
number of ReadReq hits
+system.cpu.icache.ReadReq_hits 1186515973 #
number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 40376000 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000000 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate 0.000001 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 721 #
number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 38213000
# number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 #
mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 721 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2671091.031900
# Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1645653.221914
# Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 1925857355 #
number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 1186516694 #
number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 #
average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000
# average overall mshr miss latency
-system.cpu.icache.demand_hits 1925856634 #
number of demand (read+write) hits
+system.cpu.icache.demand_hits 1186515973 #
number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 40376000 #
number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000000 #
miss rate for demand accesses
+system.cpu.icache.demand_miss_rate 0.000001 #
miss rate for demand accesses
system.cpu.icache.demand_misses 721 #
number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 38213000
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000000 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000001 #
mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 721 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1925857355 #
number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 1186516694 #
number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000
# average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1925856634 #
number of overall hits
+system.cpu.icache.overall_hits 1186515973 #
number of overall hits
system.cpu.icache.overall_miss_latency 40376000 #
number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000000 #
miss rate for overall accesses
+system.cpu.icache.overall_miss_rate 0.000001 #
miss rate for overall accesses
system.cpu.icache.overall_misses 721 #
number of overall misses
system.cpu.icache.overall_mshr_hits 0 #
number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 38213000
# number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000000 #
mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000001 #
mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 721 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
system.cpu.icache.replacements 4 #
number of replacements
system.cpu.icache.sampled_refs 721 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 658.724808 #
Cycle average of tags in use
-system.cpu.icache.total_refs 1925856634 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 659.165920 #
Cycle average of tags in use
+system.cpu.icache.total_refs 1186515973 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
system.cpu.idle_fraction 0 #
Percentage of idle cycles
@@ -194,12 +194,12 @@
system.cpu.l2cache.replacements 82097 #
number of replacements
system.cpu.l2cache.sampled_refs 97587 #
Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0
# number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16428.009263 #
Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 16488.807758 #
Cycle average of tags in use
system.cpu.l2cache.total_refs 332264 #
Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61702 #
number of writebacks
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
-system.cpu.numCycles 5108169656 #
number of cpu cycles simulated
+system.cpu.numCycles 3629488334 #
number of cpu cycles simulated
system.cpu.num_insts 1619365942 #
Number of instructions executed
system.cpu.num_refs 607148814 #
Number of memory references
system.cpu.workload.PROG:num_syscalls 48 #
Number of system calls
diff -r c92d57f579b1 -r 156cc0770e74
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
--- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout Wed Feb 25
10:18:36 2009 -0800
+++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout Wed Feb 25
10:18:45 2009 -0800
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:53:06
-M5 executing on zizzer
+M5 compiled Feb 24 2009 01:30:29
+M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
+M5 started Feb 24 2009 01:31:11
+M5 executing on tater
command line: build/SPARC_SE/m5.fast -d
build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re
tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -28,4 +28,4 @@
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 366445521000 because target called exit()
+Exiting @ tick 366435406000 because target called exit()
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
