changeset 1c9bea4afc53 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1c9bea4afc53
description:
X86: Add classes that break out the bits of the DR6 and DR7 registers.
diffstat:
1 file changed, 32 insertions(+)
src/arch/x86/miscregs.hh | 32 ++++++++++++++++++++++++++++++++
diffs (42 lines):
diff -r 516eda09c743 -r 1c9bea4afc53 src/arch/x86/miscregs.hh
--- a/src/arch/x86/miscregs.hh Wed Feb 25 10:19:47 2009 -0800
+++ b/src/arch/x86/miscregs.hh Wed Feb 25 10:19:54 2009 -0800
@@ -572,6 +572,38 @@
Bitfield<3, 0> tpr; // Task Priority Register
EndBitUnion(CR8)
+ BitUnion64(DR6)
+ Bitfield<0> b0;
+ Bitfield<1> b1;
+ Bitfield<2> b2;
+ Bitfield<3> b3;
+ Bitfield<13> bd;
+ Bitfield<14> bs;
+ Bitfield<15> bt;
+ EndBitUnion(DR6)
+
+ BitUnion64(DR7)
+ Bitfield<0> l0;
+ Bitfield<1> g0;
+ Bitfield<2> l1;
+ Bitfield<3> g1;
+ Bitfield<4> l2;
+ Bitfield<5> g2;
+ Bitfield<6> l3;
+ Bitfield<7> g3;
+ Bitfield<8> le;
+ Bitfield<9> ge;
+ Bitfield<13> gd;
+ Bitfield<17, 16> rw0;
+ Bitfield<19, 18> len0;
+ Bitfield<21, 20> rw1;
+ Bitfield<23, 22> len1;
+ Bitfield<25, 24> rw2;
+ Bitfield<27, 26> len2;
+ Bitfield<29, 28> rw3;
+ Bitfield<31, 30> len3;
+ EndBitUnion(DR7)
+
// MTRR capabilities
BitUnion64(MTRRcap)
Bitfield<7, 0> vcnt; // Variable-Range Register Count
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