changeset c182698e1ab3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c182698e1ab3
description:
X86: Add microops for reading/writing debug registers.
diffstat:
2 files changed, 58 insertions(+), 19 deletions(-)
src/arch/x86/isa/microops/regop.isa | 36 ++++++++++++++++++++++++++++++
src/arch/x86/isa/operands.isa | 41 ++++++++++++++++++-----------------
diffs (100 lines):
diff -r 1c9bea4afc53 -r c182698e1ab3 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:19:54 2009 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:20:01 2009 -0800
@@ -923,6 +923,42 @@
class Zext(RegOp):
code = 'DestReg = bits(psrc1, op2, 0);'
+ class Rddr(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Rddr, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ CR4 cr4 = CR4Op;
+ DR7 dr7 = DR7Op;
+ if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
+ fault = new InvalidOpcode();
+ } else if (dr7.gd) {
+ fault = new DebugException();
+ } else {
+ DestReg = merge(DestReg, DebugSrc1, dataSize);
+ }
+ '''
+
+ class Wrdr(RegOp):
+ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+ super(Wrdr, self).__init__(dest, \
+ src1, "NUM_INTREGS", flags, dataSize)
+ code = '''
+ CR4 cr4 = CR4Op;
+ DR7 dr7 = DR7Op;
+ if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
+ fault = new InvalidOpcode();
+ } else if ((dest == 6 || dest == 7) &&
+ bits(psrc1, 63, 32) &&
+ machInst.mode.mode == LongMode) {
+ fault = new GeneralProtection(0);
+ } else if (dr7.gd) {
+ fault = new DebugException();
+ } else {
+ DebugDest = psrc1;
+ }
+ '''
+
class Rdcr(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rdcr, self).__init__(dest, \
diff -r 1c9bea4afc53 -r c182698e1ab3 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Wed Feb 25 10:19:54 2009 -0800
+++ b/src/arch/x86/isa/operands.isa Wed Feb 25 10:20:01 2009 -0800
@@ -138,28 +138,31 @@
# original instruction.
'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
- 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
- 'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
- 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)',
(None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
- 'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)',
(None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
- 'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
- 'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
- 'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
- 'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
+ 'DebugDest': ('ControlReg', 'uqw', 'MISCREG_DR(dest)', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
+ 'DebugSrc1': ('ControlReg', 'uqw', 'MISCREG_DR(src1)', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
+ 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
+ 'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
+ 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)',
(None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
+ 'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)',
(None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
+ 'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
+ 'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
+ 'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 110),
+ 'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 111),
# Operands to access specific control registers directly.
'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200),
'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201),
- 'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
- 'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
- 'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
- 'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
- 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
- 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
- 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
- 'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
- 'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
- 'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None,
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
- 'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None,
None), 212),
+ 'DR7Op': ('ControlReg', 'uqw', 'MISCREG_DR7', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
+ 'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
+ 'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
+ 'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
+ 'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
+ 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
+ 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None,
None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
+ 'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
+ 'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
+ 'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None,
['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 211),
+ 'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None,
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 212),
+ 'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None,
None), 213),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad',
'IsStore'), 300)
}};
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