changeset 80c3baea7444 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=80c3baea7444 description: X86: Update stats now that prefetch is implemented.
diffstat: 6 files changed, 106 insertions(+), 123 deletions(-) tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr | 8 tests/long/00.gzip/ref/x86/linux/simple-atomic/simout | 7 tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt | 10 tests/long/00.gzip/ref/x86/linux/simple-timing/simerr | 8 tests/long/00.gzip/ref/x86/linux/simple-timing/simout | 8 tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt | 188 +++++++------- diffs (truncated from 367 to 300 lines): diff -r 5a9c976270d6 -r 80c3baea7444 tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr Wed Feb 25 10:19:22 2009 -0800 +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr Wed Feb 25 10:19:28 2009 -0800 @@ -4,12 +4,4 @@ For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff -r 5a9c976270d6 -r 80c3baea7444 tests/long/00.gzip/ref/x86/linux/simple-atomic/simout --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout Wed Feb 25 10:19:22 2009 -0800 +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout Wed Feb 25 10:19:28 2009 -0800 @@ -5,9 +5,9 @@ All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 22:05:32 +M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch +M5 started Feb 24 2009 22:07:57 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -26,7 +26,6 @@ Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data -info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 diff -r 5a9c976270d6 -r 80c3baea7444 tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt Wed Feb 25 10:19:22 2009 -0800 +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt Wed Feb 25 10:19:28 2009 -0800 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 977325 # Simulator instruction rate (inst/s) -host_mem_usage 197144 # Number of bytes of host memory used -host_seconds 1656.94 # Real time elapsed on the host -host_tick_rate 581149945 # Simulator tick rate (ticks/s) +host_inst_rate 1045935 # Simulator instruction rate (inst/s) +host_mem_usage 197296 # Number of bytes of host memory used +host_seconds 1548.25 # Real time elapsed on the host +host_tick_rate 621947296 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated sim_seconds 0.962929 # Number of seconds simulated @@ -12,7 +12,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1925857354 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed -system.cpu.num_refs 607148814 # Number of memory references +system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 5a9c976270d6 -r 80c3baea7444 tests/long/00.gzip/ref/x86/linux/simple-timing/simerr --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr Wed Feb 25 10:19:22 2009 -0800 +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simerr Wed Feb 25 10:19:28 2009 -0800 @@ -4,12 +4,4 @@ For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 -warn: instruction 'prefetch_t0' unimplemented -For more information see: http://www.m5sim.org/warn/437d5238 hack: be nice to actually delete the event here diff -r 5a9c976270d6 -r 80c3baea7444 tests/long/00.gzip/ref/x86/linux/simple-timing/simout --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout Wed Feb 25 10:19:22 2009 -0800 +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout Wed Feb 25 10:19:28 2009 -0800 @@ -5,9 +5,9 @@ All Rights Reserved -M5 compiled Feb 24 2009 01:30:29 -M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch -M5 started Feb 24 2009 01:41:46 +M5 compiled Feb 24 2009 22:05:32 +M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch +M5 started Feb 24 2009 22:07:57 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -44,4 +44,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1814744167000 because target called exit() +Exiting @ tick 1814896671000 because target called exit() diff -r 5a9c976270d6 -r 80c3baea7444 tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt Wed Feb 25 10:19:22 2009 -0800 +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt Wed Feb 25 10:19:28 2009 -0800 @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 759916 # Simulator instruction rate (inst/s) -host_mem_usage 204700 # Number of bytes of host memory used -host_seconds 2130.98 # Real time elapsed on the host -host_tick_rate 851601124 # Simulator tick rate (ticks/s) +host_inst_rate 660241 # Simulator instruction rate (inst/s) +host_mem_usage 204740 # Number of bytes of host memory used +host_seconds 2452.69 # Real time elapsed on the host +host_tick_rate 739961389 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated -sim_seconds 1.814744 # Number of seconds simulated -sim_ticks 1814744167000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 418768378 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4088840000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000464 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 194380 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3505700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000464 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 194380 # number of ReadReq MSHR misses +sim_seconds 1.814897 # Number of seconds simulated +sim_ticks 1814896671000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 20939.027041 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17939.027041 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 418844309 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4141928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000472 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 197809 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3548501000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000472 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 197809 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187874337 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17456264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 311719 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16521107000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001656 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 311719 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 187873910 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17480176000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001659 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 312146 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16543738000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001659 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 312146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1367.059283 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1364.014744 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 607148814 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606642715 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21545104000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses -system.cpu.dcache.demand_misses 506099 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 42400.023531 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606718219 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21622104000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000840 # miss rate for demand accesses +system.cpu.dcache.demand_misses 509955 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20026807000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 506099 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 20092239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000840 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 509955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 607148814 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42570.927822 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39570.927822 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 42400.023531 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606642715 # number of overall hits -system.cpu.dcache.overall_miss_latency 21545104000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses -system.cpu.dcache.overall_misses 506099 # number of overall misses +system.cpu.dcache.overall_hits 606718219 # number of overall hits +system.cpu.dcache.overall_miss_latency 21622104000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000840 # miss rate for overall accesses +system.cpu.dcache.overall_misses 509955 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20026807000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 20092239000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000840 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 509955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 439707 # number of replacements -system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 440755 # number of replacements +system.cpu.dcache.sampled_refs 444851 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.900260 # Cycle average of tags in use -system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.900352 # Cycle average of tags in use +system.cpu.dcache.total_refs 606783323 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 308507 # number of writebacks +system.cpu.dcache.writebacks 308934 # number of writebacks system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -120,88 +120,88 @@ system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 659.165920 # Cycle average of tags in use +system.cpu.icache.tagsinuse 659.162719 # Cycle average of tags in use system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 249423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247042 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12969996000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 12846184000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 249423 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9976920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 247042 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9881680000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 249423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 195101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 247042 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 198530 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 161820 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1730612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170583 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1331240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33281 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 62296 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 165128 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1736904000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.168247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33402 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1336080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.168247 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33402 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 65104 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3239392000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3385408000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 62296 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2491840000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 65104 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2604160000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 62296 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 308507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 308507 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 65104 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 308934 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.404798 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.437930 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
