changeset 28bcb158eaae in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=28bcb158eaae
description:
CPU: Add a flag to identify a read barrier to the static inst class.
diffstat:
1 file changed, 1 insertion(+)
src/cpu/static_inst.hh | 1 +
diffs (11 lines):
diff -r 80c3baea7444 -r 28bcb158eaae src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh Wed Feb 25 10:19:28 2009 -0800
+++ b/src/cpu/static_inst.hh Wed Feb 25 10:19:33 2009 -0800
@@ -159,6 +159,7 @@
IsSerializeAfter,
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
+ IsReadBarrier, ///< Is a read barrier
IsERET, /// <- Causes the IFU to stall (MIPS ISA)
IsNonSpeculative, ///< Should not be executed speculatively
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