changeset 410d14f82f13 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=410d14f82f13
description:
X86: Fix a few bugs with the segment register instructions in real mode.
Fix a few instances where the register form of zext was used where
zexti was
intended. Also get rid of the 64 bit only rip relative addressed
version since
64 bit and real mode are mutually exclusive.
diffstat:
1 file changed, 3 insertions(+), 8 deletions(-)
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 11 ++--------
diffs (34 lines):
diff -r 5e3367b103da -r 410d14f82f13
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:20:10 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:20:19 2009 -0800
@@ -215,7 +215,7 @@
};
def macroop MOV_REAL_S_R {
- zext t2, regm, 15, dataSize=8
+ zexti t2, regm, 15, dataSize=8
slli t3, t2, 2, dataSize=8
wrsel reg, regm
wrbase reg, t3
@@ -223,19 +223,14 @@
def macroop MOV_REAL_S_M {
ld t1, seg, sib, disp, dataSize=2
- zext t2, t1, 15, dataSize=8
+ zexti t2, t1, 15, dataSize=8
slli t3, t2, 2, dataSize=8
wrsel reg, t1
wrbase reg, t3
};
def macroop MOV_REAL_S_P {
- rdip t7
- ld t1, seg, riprel, disp, dataSize=2
- zext t2, t1, 15, dataSize=8
- slli t3, t2, 2, dataSize=8
- wrsel reg, t1
- wrbase reg, t3
+ panic "RIP relative addressing shouldn't happen in real mode"
};
def macroop MOV_S_R {
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